From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4923 invoked by alias); 31 Oct 2019 09:35:37 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 4903 invoked by uid 89); 31 Oct 2019 09:35:36 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,MIME_CHARSET_FARAWAY,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy=launched, Kewen, kewen, Lin X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 31 Oct 2019 09:35:33 +0000 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9V9JMYk141258 for ; Thu, 31 Oct 2019 05:35:31 -0400 Received: from e06smtp03.uk.ibm.com (e06smtp03.uk.ibm.com [195.75.94.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vyu6pv7fx-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 31 Oct 2019 05:35:31 -0400 Received: from localhost by e06smtp03.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 31 Oct 2019 09:35:27 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9V9ZPJ145875238 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 31 Oct 2019 09:35:25 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 52A30AE057; Thu, 31 Oct 2019 09:35:25 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC36FAE04D; Thu, 31 Oct 2019 09:35:23 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.202]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 31 Oct 2019 09:35:23 +0000 (GMT) Subject: [PATCH 3/3 V2][rs6000] vector conversion RTL pattern update for diff unit size To: Segher Boessenkool Cc: GCC Patches , Bill Schmidt References: <172addbc-3aae-084b-cce4-b9c8a194821d@linux.ibm.com> <22fd6de1-dc31-a977-a803-0a2cb3f11444@linux.ibm.com> <20191030184929.GM28442@gate.crashing.org> From: "Kewen.Lin" Date: Thu, 31 Oct 2019 09:35:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20191030184929.GM28442@gate.crashing.org> Content-Type: multipart/mixed; boundary="------------D470227B49D168E1DC49007E" x-cbid: 19103109-0012-0000-0000-0000035F6D93 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19103109-0013-0000-0000-0000219AB767 Message-Id: X-IsSubscribed: yes X-SW-Source: 2019-10/txt/msg02210.txt.bz2 This is a multi-part message in MIME format. --------------D470227B49D168E1DC49007E Content-Type: text/plain; charset=gbk Content-Transfer-Encoding: 8bit Content-length: 3284 Hi Segher, Thanks a lot for the comments. on 2019/10/31 ÉÏÎç2:49, Segher Boessenkool wrote: > Hi! > > On Wed, Oct 23, 2019 at 05:42:45PM +0800, Kewen.Lin wrote: >> Following the previous one 2/3, this patch is to update the >> vector conversions between fixed point and floating point >> with different element unit sizes, such as: SP <-> DI, DP <-> SI. > >> (vsx_xvcvdp[su]xws): New define_expand, old one split to... > > You mean here, please fix (never use wildcards like [su] in changelogs: > people grep for things in changelogs, which misses entries with wildcards). > OK, will fix it. >> +/* Half VMX/VSX vector (for select) */ >> +VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ >> +VECTOR_MODE (INT, SI, 2); /* V2SI */ > > Or "for internal use", in general. What happens if a user tries to create > something of such a mode? I hope we don't ICE :-/ > I did some testings, it failed (ICE) if we constructed one insn with these modes artificially. But I also checked the existing V8SF/V8SI/V4DF/... etc., they have same issues. It looks more like a new issue to avoid that. >> +;; Convert vector of 64-bit floating point numbers to vector of >> +;; 32-bit signed/unsigned integers. >> +(define_insn "vsx_xvcvdpxws_be" >> [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa") >> - (unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")] >> - UNSPEC_VSX_CVDPSXWS))] >> - "VECTOR_UNIT_VSX_P (V2DFmode)" >> - "xvcvdpsxws %x0,%x1" >> + (any_fix:V4SI >> + (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa") >> + (vec_select:V2DF (match_dup 1) >> + (parallel [(const_int 1) (const_int 0)])))))] >> + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" >> + "xvcvdpxws %x0,%x1" >> [(set_attr "type" "vecdouble")]) > > This doesn't work, I think: the insns actually leaves words 1 and 3 > undefined, but this pattern gives them a meaning. > > I don't think we can do better than unspecs for such insns. Or change > the pattern to only describe the defined parts (this works for e.g. mulhw > that describes its result as SImode: its DImode result has the high half > undefined). > Good point, thanks! I agree, the current implementation for 64bit -> 32bit RTL pattern has different semantics to what the instructions represent. I was trying to find something represent undefined or random register value and with twice vec_concat, but failed to. I'll recover the change for the 64bit -> 32bit part. Updated patch attached, new regression testing just launched. BR, Kewen ----------------- gcc/ChangeLog 2019-10-31 Kewen Lin * config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes. * config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove. (vsx_xvcvspdp): New define_expand, old define_insn split to... (vsx_xvcvspdp_be): ... this. New. And... (vsx_xvcvspdp_le): ... this. New. (vsx_xvcvxwdp): New define_expand, old define_insn split to... (vsx_xvcvxwdp_be): ... this. New. And... (vsx_xvcvxwdp_le): ... this. New. (vsx_xvcvspxds): New define_expand, old define_insn split to... (vsx_xvcvspxds_be): ... this. New. And... (vsx_xvcvspxds_le): ... this. New. --------------D470227B49D168E1DC49007E Content-Type: text/plain; charset=UTF-8; x-mac-type="0"; x-mac-creator="0"; name="unspecv2.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="unspecv2.diff" Content-length: 6594 diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def index 677062c..2051358 100644 --- a/gcc/config/rs6000/rs6000-modes.def +++ b/gcc/config/rs6000/rs6000-modes.def @@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */ VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */ VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */ +/* Half VMX/VSX vector (for internal use) */ +VECTOR_MODE (FLOAT, SF, 2); /* V2SF */ +VECTOR_MODE (INT, SI, 2); /* V2SI */ + /* Replacement for TImode that only is allowed in GPRs. We also use PTImode for quad memory atomic operations to force getting an even/odd register combination. */ diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 83e4071..99b51cb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -275,8 +275,6 @@ UNSPEC_VSX_CVUXWDP UNSPEC_VSX_CVSXDSP UNSPEC_VSX_CVUXDSP - UNSPEC_VSX_CVSPSXDS - UNSPEC_VSX_CVSPUXDS UNSPEC_VSX_FLOAT2 UNSPEC_VSX_UNS_FLOAT2 UNSPEC_VSX_FLOATE @@ -2106,14 +2104,36 @@ "xscvdpsp %x0,%x1" [(set_attr "type" "fp")]) -(define_insn "vsx_xvcvspdp" +(define_insn "vsx_xvcvspdp_be" [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPDP))] - "VECTOR_UNIT_VSX_P (V4SFmode)" + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN" + "xvcvspdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_insn "vsx_xvcvspdp_le" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa") + (float_extend:V2DF + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN" "xvcvspdp %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_expand "vsx_xvcvspdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand")] + "VECTOR_UNIT_VSX_P (V4SFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1])); + DONE; +}) + (define_insn "vsx_xvcvdpsp" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa") (unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")] @@ -2333,16 +2353,39 @@ "xvcvuxdsp %x0,%x1" [(set_attr "type" "vecdouble")]) -;; Convert from 32-bit to 64-bit types -;; Provide both vector and scalar targets -(define_insn "vsx_xvcvsxwdp" +;; Convert vector of 32-bit signed/unsigned integers to vector of +;; 64-bit floating point numbers. +(define_insn "vsx_xvcvxwdp_be" [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVSXWDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvsxwdp %x0,%x1" + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_insn "vsx_xvcvxwdp_le" + [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") + (any_float:V2DF + (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvxwdp %x0,%x1" + [(set_attr "type" "vecdouble")]) + +(define_expand "vsx_xvcvxwdp" + [(match_operand:V2DF 0 "vsx_register_operand") + (match_operand:V4SI 1 "vsx_register_operand") + (any_float (pc))] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvxwdp_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvxwdp_le (operands[0], operands[1])); + DONE; +}) + (define_insn "vsx_xvcvsxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2351,14 +2394,6 @@ "xvcvsxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvuxwdp" - [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa") - (unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] - UNSPEC_VSX_CVUXWDP))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvuxwdp %x0,%x1" - [(set_attr "type" "vecdouble")]) - (define_insn "vsx_xvcvuxwdp_df" [(set (match_operand:DF 0 "vsx_register_operand" "=wa") (unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")] @@ -2367,22 +2402,39 @@ "xvcvuxwdp %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvspsxds" +;; Convert vector of 32-bit floating point numbers to vector of +;; 64-bit signed/unsigned integers. +(define_insn "vsx_xvcvspxds_be" [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPSXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspsxds %x0,%x1" + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 0) (const_int 2)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" [(set_attr "type" "vecdouble")]) -(define_insn "vsx_xvcvspuxds" +(define_insn "vsx_xvcvspxds_le" [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa") - (unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] - UNSPEC_VSX_CVSPUXDS))] - "VECTOR_UNIT_VSX_P (V2DFmode)" - "xvcvspuxds %x0,%x1" + (any_fix:V2DI + (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (parallel [(const_int 1) (const_int 3)]))))] + "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN" + "xvcvspxds %x0,%x1" [(set_attr "type" "vecdouble")]) +(define_expand "vsx_xvcvspxds" + [(match_operand:V2DI 0 "vsx_register_operand") + (match_operand:V4SF 1 "vsx_register_operand") + (any_fix (pc))] + "VECTOR_UNIT_VSX_P (V2DFmode)" +{ + if (BYTES_BIG_ENDIAN) + emit_insn (gen_vsx_xvcvspxds_be (operands[0], operands[1])); + else + emit_insn (gen_vsx_xvcvspxds_le (operands[0], operands[1])); + DONE; +}) + ;; Generate float2 double ;; convert two double to float (define_expand "float2_v2df" --------------D470227B49D168E1DC49007E--