From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 102815 invoked by alias); 15 Dec 2017 11:57:58 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 102795 invoked by uid 89); 15 Dec 2017 11:57:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-21.2 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_SHORT,MEDICAL_SUBJECT,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Exchange-Antispam-Report-Test:131327999870524 X-HELO: EUR01-DB5-obe.outbound.protection.outlook.com Received: from mail-eopbgr60050.outbound.protection.outlook.com (HELO EUR01-DB5-obe.outbound.protection.outlook.com) (40.107.6.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 15 Dec 2017 11:57:54 +0000 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Sudi.Das@arm.com; Received: from [10.2.206.246] (217.140.96.140) by VI1PR08MB1056.eurprd08.prod.outlook.com (2a01:111:e400:c549::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.323.15; Fri, 15 Dec 2017 11:57:49 +0000 To: "gcc-patches@gcc.gnu.org" Cc: nd , James Greenhalgh , Richard Earnshaw , Marcus Shawcroft From: Sudakshina Das Subject: [PATCH PR81647][AARCH64] Fix handling of Unordered Comparisons in aarch64-simd.md Message-ID: Date: Fri, 15 Dec 2017 11:57:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.0 MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="------------FD451D940461BDB41CE23FFB" X-ClientProxiedBy: AM4PR05CA0016.eurprd05.prod.outlook.com (2603:10a6:205::29) To VI1PR08MB1056.eurprd08.prod.outlook.com (2a01:111:e400:c549::20) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 22405a86-08cc-42ac-734e-08d543b3108e X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:(5600026)(4604075)(4534020)(4602075)(4627115)(201703031133081)(201702281549075)(48565401081)(2017052603307)(49563074);SRVR:VI1PR08MB1056; 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charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 1550 Hi This patch fixes the inconsistent behavior observed at -O3 for the unordered comparisons. According to the online docs (https://gcc.gnu.org/onlinedocs/gcc-7.2.0/gccint/Unary-and-Binary-Expressions.html), all of the following should not raise an FP exception: - UNGE_EXPR - UNGT_EXPR - UNLE_EXPR - UNLT_EXPR - UNEQ_EXPR Also ORDERED_EXPR and UNORDERED_EXPR should only return zero or one. The aarch64-simd.md handling of these were generating exception raising instructions such as fcmgt. This patch changes the instructions that are emitted to in order to not give out the exceptions. We first check each operand for NaNs and force any elements containing NaN to zero before using them in the compare. Example: UN (a, b) -> UNORDERED (a, b) | (cm (isnan (a) ? 0.0 : a, isnan (b) ? 0.0 : b)) The ORDERED_EXPR is now handled as (cmeq (a, a) & cmeq (b, b)) and UNORDERED_EXPR as ~ORDERED_EXPR and UNEQ as (~ORDERED_EXPR | cmeq (a,b)). Testing done: Checked for regressions on bootstrapped aarch64-none-linux-gnu and added a new test case. Is this ok for trunk? This will probably need a back-port to gcc-7-branch as well. Thanks Sudi ChangeLog Entries: *** gcc/ChangeLog *** 2017-12-15 Sudakshina Das PR target/81647 * config/aarch64/aarch64-simd.md (vec_cmp): Modify instructions for UNLT, UNLE, UNGT, UNGE, UNEQ, UNORDERED and ORDERED. *** gcc/testsuite/ChangeLog *** 2017-12-15 Sudakshina Das PR target/81647 * gcc.target/aarch64/pr81647.c: New. --------------FD451D940461BDB41CE23FFB Content-Type: text/x-patch; name="rb8660.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="rb8660.patch" Content-length: 7037 diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f90f74fe7fd5990a97b9f4eb68f5735b7d4fb9aa..acff06c753b3e3aaa5775632929909afa4d3294b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2731,10 +2731,10 @@ break; } /* Fall through. */ - case UNGE: + case UNLT: std::swap (operands[2], operands[3]); /* Fall through. */ - case UNLE: + case UNGT: case GT: comparison = gen_aarch64_cmgt; break; @@ -2745,10 +2745,10 @@ break; } /* Fall through. */ - case UNGT: + case UNLE: std::swap (operands[2], operands[3]); /* Fall through. */ - case UNLT: + case UNGE: case GE: comparison = gen_aarch64_cmge; break; @@ -2771,21 +2771,35 @@ case UNGT: case UNLE: case UNLT: - case NE: - /* FCM returns false for lanes which are unordered, so if we use - the inverse of the comparison we actually want to emit, then - invert the result, we will end up with the correct result. - Note that a NE NaN and NaN NE b are true for all a, b. - - Our transformations are: - a UNGE b -> !(b GT a) - a UNGT b -> !(b GE a) - a UNLE b -> !(a GT b) - a UNLT b -> !(a GE b) - a NE b -> !(a EQ b) */ - gcc_assert (comparison != NULL); - emit_insn (comparison (operands[0], operands[2], operands[3])); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + { + /* All of the above must not raise any FP exceptions. Thus we first + check each operand for NaNs and force any elements containing NaN to + zero before using them in the compare. + Example: UN (a, b) -> UNORDERED (a, b) | + (cm (isnan (a) ? 0.0 : a, + isnan (b) ? 0.0 : b)) + We use the following transformations for doing the comparisions: + a UNGE b -> a GE b + a UNGT b -> a GT b + a UNLE b -> b GE a + a UNLT b -> b GT a. */ + + rtx tmp0 = gen_reg_rtx (mode); + rtx tmp1 = gen_reg_rtx (mode); + rtx tmp2 = gen_reg_rtx (mode); + emit_insn (gen_aarch64_cmeq (tmp0, operands[2], operands[2])); + emit_insn (gen_aarch64_cmeq (tmp1, operands[3], operands[3])); + emit_insn (gen_and3 (tmp2, tmp0, tmp1)); + emit_insn (gen_and3 (tmp0, tmp0, + lowpart_subreg (mode, operands[2], mode))); + emit_insn (gen_and3 (tmp1, tmp1, + lowpart_subreg (mode, operands[3], mode))); + gcc_assert (comparison != NULL); + emit_insn (comparison (operands[0], + lowpart_subreg (mode, tmp0, mode), + lowpart_subreg (mode, tmp1, mode))); + emit_insn (gen_orn3 (operands[0], tmp2, operands[0])); + } break; case LT: @@ -2793,25 +2807,19 @@ case GT: case GE: case EQ: + case NE: /* The easy case. Here we emit one of FCMGE, FCMGT or FCMEQ. As a LT b <=> b GE a && a LE b <=> b GT a. Our transformations are: a GE b -> a GE b a GT b -> a GT b a LE b -> b GE a a LT b -> b GT a - a EQ b -> a EQ b */ + a EQ b -> a EQ b + a NE b -> ~(a EQ b) */ gcc_assert (comparison != NULL); emit_insn (comparison (operands[0], operands[2], operands[3])); - break; - - case UNEQ: - /* We first check (a > b || b > a) which is !UNEQ, inverting - this result will then give us (a == b || a UNORDERED b). */ - emit_insn (gen_aarch64_cmgt (operands[0], - operands[2], operands[3])); - emit_insn (gen_aarch64_cmgt (tmp, operands[3], operands[2])); - emit_insn (gen_ior3 (operands[0], operands[0], tmp)); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + if (code == NE) + emit_insn (gen_one_cmpl2 (operands[0], operands[0])); break; case LTGT: @@ -2823,21 +2831,22 @@ emit_insn (gen_ior3 (operands[0], operands[0], tmp)); break; - case UNORDERED: - /* Operands are ORDERED iff (a > b || b >= a), so we can compute - UNORDERED as !ORDERED. */ - emit_insn (gen_aarch64_cmgt (tmp, operands[2], operands[3])); - emit_insn (gen_aarch64_cmge (operands[0], - operands[3], operands[2])); - emit_insn (gen_ior3 (operands[0], operands[0], tmp)); - emit_insn (gen_one_cmpl2 (operands[0], operands[0])); - break; - case ORDERED: - emit_insn (gen_aarch64_cmgt (tmp, operands[2], operands[3])); - emit_insn (gen_aarch64_cmge (operands[0], - operands[3], operands[2])); - emit_insn (gen_ior3 (operands[0], operands[0], tmp)); + case UNORDERED: + case UNEQ: + /* cmeq (a, a) & cmeq (b, b). */ + emit_insn (gen_aarch64_cmeq (operands[0], + operands[2], operands[2])); + emit_insn (gen_aarch64_cmeq (tmp, operands[3], operands[3])); + emit_insn (gen_and3 (operands[0], operands[0], tmp)); + + if (code == UNORDERED) + emit_insn (gen_one_cmpl2 (operands[0], operands[0])); + else if (code == UNEQ) + { + emit_insn (gen_aarch64_cmeq (tmp, operands[2], operands[3])); + emit_insn (gen_orn3 (operands[0], operands[0], tmp)); + } break; default: diff --git a/gcc/testsuite/gcc.target/aarch64/pr81647.c b/gcc/testsuite/gcc.target/aarch64/pr81647.c new file mode 100644 index 0000000000000000000000000000000000000000..f60dfba49d538e3b2164b11392ab8dbfdba6546e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr81647.c @@ -0,0 +1,44 @@ +/* { dg-do run } */ +/* { dg-options "-O3 -fdump-tree-ssa" } */ + +#include + +double x[28], y[28]; +int res[28]; + +int +main (void) +{ + int i; + for (i = 0; i < 28; ++i) + { + x[i] = __builtin_nan (""); + y[i] = i; + } + __asm__ volatile ("" ::: "memory"); + feclearexcept (FE_ALL_EXCEPT); + for (i = 0; i < 4; ++i) + res[i] = __builtin_isgreater (x[i], y[i]); + for (i = 4; i < 8; ++i) + res[i] = __builtin_isgreaterequal (x[i], y[i]); + for (i = 8; i < 12; ++i) + res[i] = __builtin_isless (x[i], y[i]); + for (i = 12; i < 16; ++i) + res[i] = __builtin_islessequal (x[i], y[i]); + for (i = 16; i < 20; ++i) + res[i] = __builtin_islessgreater (x[i], y[i]); + for (i = 20; i < 24; ++i) + res[i] = __builtin_isunordered (x[i], y[i]); + for (i = 24; i < 28; ++i) + res[i] = !(__builtin_isunordered (x[i], y[i])); + __asm__ volatile ("" ::: "memory"); + return fetestexcept (FE_ALL_EXCEPT) != 0; +} + +/* { dg-final { scan-tree-dump " u> " "ssa" } } */ +/* { dg-final { scan-tree-dump " u>= " "ssa" } } */ +/* { dg-final { scan-tree-dump " u< " "ssa" } } */ +/* { dg-final { scan-tree-dump " u<= " "ssa" } } */ +/* { dg-final { scan-tree-dump " u== " "ssa" } } */ +/* { dg-final { scan-tree-dump " unord " "ssa" } } */ +/* { dg-final { scan-tree-dump " ord " "ssa" } } */ --------------FD451D940461BDB41CE23FFB--