From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from xry111.site (xry111.site [IPv6:2001:470:683e::1]) by sourceware.org (Postfix) with ESMTPS id CB89A38582BA for ; Fri, 8 Jul 2022 13:18:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CB89A38582BA Received: from localhost.localdomain (xry111.site [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id D9C436687C; Fri, 8 Jul 2022 09:18:44 -0400 (EDT) Message-ID: Subject: [PATCH] loongarch: fix mulsidi3_64bit instruction From: Xi Ruoyao To: gcc-patches@gcc.gnu.org Cc: Lulu Cheng , Chenghua Xu , Wang Xuerui Date: Fri, 08 Jul 2022 21:18:43 +0800 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.3 MIME-Version: 1.0 X-Spam-Status: No, score=-7.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, FROM_SUSPICIOUS_NTLD_FP, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 08 Jul 2022 13:18:51 -0000 I think this should be obvious. Ok for trunk and gcc-12 branch? (Note: this bug really amazed me. It's just a simple typo and all of us failed to spot it reviewing the LoongArch port. Incredibly, it can be reproduced with such a simple test case (in the patch) but did not blow the entire system up. I didn't see anything abnormal until it blown up two UBSan test cases when I tried to port UBSan for LoongArch.) -- >8 -- (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be "mulw.d.w", not "mul.d". gcc/ChangeLog: * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w instead of mul.d. gcc/testsuite/ChangeLog: * gcc.target/loongarch/mul-1.c: New test. * gcc.target/loongarch/mul-2.c: New test. --- gcc/config/loongarch/loongarch.md | 2 +- gcc/testsuite/gcc.target/loongarch/mul-1.c | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/loongarch/mul-2.c | 10 ++++++++++ 3 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/mul-1.c create mode 100644 gcc/testsuite/gcc.target/loongarch/mul-2.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loong= arch.md index d3c809e25f3..8f8412fba84 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -621,7 +621,7 @@ (define_insn "mulsidi3_64bit" (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_64BIT" - "mul.d\t%0,%1,%2" + "mulw.d.w\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) =20 diff --git a/gcc/testsuite/gcc.target/loongarch/mul-1.c b/gcc/testsuite/gcc= .target/loongarch/mul-1.c new file mode 100644 index 00000000000..8b6800804fb --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mul-1.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ + +typedef __INT64_TYPE__ int64_t; +typedef __INT32_TYPE__ int32_t; + +/* f() was misoptimized to a single "mul.d" instruction on LA64. */ +__attribute__((noipa, noinline)) int64_t +f(int64_t a, int64_t b) +{ + return (int64_t)(int32_t)a * (int64_t)(int32_t)b; +} + +int +main() +{ + int64_t a =3D 0x1145140000000001; + int64_t b =3D 0x1919810000000001; + if (f(a, b) !=3D 1) + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.target/loongarch/mul-2.c b/gcc/testsuite/gcc= .target/loongarch/mul-2.c new file mode 100644 index 00000000000..a9a713210df --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mul-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=3Dlp64d" } */ +/* { dg-final { scan-assembler "mulw.d.w\t\\\$r4,\\\$r5,\\\$r4" } } */ + +/* This should be optimized to mulw.d.w for LA64. */ +__attribute__((noipa, noinline)) long +f(long a, long b) +{ + return (long)(int)a * (long)(int)b; +} --=20 2.37.0