From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 6437 invoked by alias); 11 Dec 2009 22:26:57 -0000 Received: (qmail 6427 invoked by uid 22791); 11 Dec 2009 22:26:56 -0000 X-SWARE-Spam-Status: No, hits=-1.8 required=5.0 tests=AWL,BAYES_00,SARE_MSGID_LONG40,SPF_PASS X-Spam-Check-By: sourceware.org Received: from mail-ew0-f214.google.com (HELO mail-ew0-f214.google.com) (209.85.219.214) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 11 Dec 2009 22:26:52 +0000 Received: by ewy6 with SMTP id 6so4196ewy.29 for ; Fri, 11 Dec 2009 14:26:50 -0800 (PST) MIME-Version: 1.0 Received: by 10.213.57.136 with SMTP id c8mr69476ebh.11.1260570410273; Fri, 11 Dec 2009 14:26:50 -0800 (PST) In-Reply-To: <20091211213422.GJ22813@hs20-bc2-1.build.redhat.com> References: <20091009003847.13926.38424.sendpatchset@tilapia-05.site> <20091105162124.GS14664@tyan-ft48-01.lab.bos.redhat.com> <20091106101131.GW14664@tyan-ft48-01.lab.bos.redhat.com> <20091210200641.GE22813@hs20-bc2-1.build.redhat.com> <20091210210945.GF22813@hs20-bc2-1.build.redhat.com> <20091211145001.GI22813@hs20-bc2-1.build.redhat.com> <20091211213422.GJ22813@hs20-bc2-1.build.redhat.com> From: Sebastian Pop Date: Fri, 11 Dec 2009 22:27:00 -0000 Message-ID: Subject: Re: PATCH: Add LWP support for upcoming AMD Orochi processor. To: Jakub Jelinek Cc: Richard Henderson , gcc-patches@gcc.gnu.org, Uros Bizjak Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2009-12/txt/msg00641.txt.bz2 On Fri, Dec 11, 2009 at 15:34, Jakub Jelinek wrote: > Are those other people ok with the lwpintrin.h changes (primarily only > one intrinsics without number instead of 3 for llwpcb/slwpcb)? Yes, I got the ok for the current llwpcb/slwpcb intrinsics. > Is the return value from __lwpins the expected one (i.e. setc %al rather > than say setnc %al)? > They recommended to use "setb %al", but I am seeing from the manual that this is similar to "setc %al" as you implemented it. > I've briefly looked at the lengths of lwpins and lwpval insns and > the following worked well in all cases I've tried. > > If you are ok with these, can you combine the 3 patches posted today, > write ChangeLog, test it and submit? > Yes, I will do this. > OT, wonder why x86-64-lwp.[sd] in gas testsuite only tests addr32 modes, Hmm... I don't know, I will give a look at the testsuite, and I will add more testcases as needed. > which are very unlikely to occur in 64-bit code, and not normal addresses > with 64-bit base/index registers. > > --- gcc/config/i386/i386.md.jj =C2=A02009-12-11 15:38:16.000000000 +0100 > +++ gcc/config/i386/i386.md =C2=A0 =C2=A0 2009-12-11 22:26:42.000000000 += 0100 > @@ -20889,7 +20889,8 @@ (define_insn "*lwp_lwpval3_1" > =C2=A0 "lwpval\t{%2, %1, %0|%0, %1, %2}" > =C2=A0 [(set_attr "type" "lwp") > =C2=A0 =C2=A0(set_attr "mode" "") > - =C2=A0 (set_attr "length" "9")]) > + =C2=A0 (set (attr "length") > + =C2=A0 =C2=A0 =C2=A0 (symbol_ref "ix86_attr_length_address_default (ins= n) + 9"))]) > > =C2=A0(define_expand "lwp_lwpins3" > =C2=A0 [(set (reg:CCC FLAGS_REG) > @@ -20912,7 +20913,8 @@ (define_insn "*lwp_lwpins3_1" > =C2=A0 "lwpins\t{%2, %1, %0|%0, %1, %2}" > =C2=A0 [(set_attr "type" "lwp") > =C2=A0 =C2=A0(set_attr "mode" "") > - =C2=A0 (set_attr "length" "9")]) > + =C2=A0 (set (attr "length") > + =C2=A0 =C2=A0 =C2=A0 (symbol_ref "ix86_attr_length_address_default (ins= n) + 9"))]) > > =C2=A0(include "mmx.md") > =C2=A0(include "sse.md") > > > =C2=A0 =C2=A0 =C2=A0 =C2=A0Jakub > Many thanks for your help, Sebastian Pop -- AMD / Open Source Compiler Engineering / GNU Tools