From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id A6E16397067E for ; Thu, 8 Dec 2022 08:47:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A6E16397067E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 2B88l748013918; Thu, 8 Dec 2022 08:47:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=5H5eZLxKcsgqlkkwO8cuwAYQP/HRJ4SmJpxia5PAaZc=; b=S3qqL8jpHVz31aZdjPDZNtAD3mDAF6bycYWqaUpB9u7NTqaBGkC/B8l6QR5kVNwBA/fP qA7fQsG+4w3/hC1aM34DYYjg7KMyguq9igRNbuZDrwDSWETAxWCX3Dcjc7eRkaqp42GP d+BMU49dptHkNlDGDCsbdbUC0GOS+tPuWnFfdE61fD1mssRTyGC4T5k1oH3NhUgxsOc5 LR3KiFUXePtdM+Y18C9vsxPmZH2OHiMnWk4ceDZ9L49F/dsHY3mE2FY1GsPtaumCCZna aZIr8rS1/wbBNLrhW2AAja3wiPg6l+8Zcg0ihFTSzLG97cCD5xtkYpqdKBGaw3vTSGfB mQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3mbcqjg09m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Dec 2022 08:47:34 +0000 Received: from m0098417.ppops.net (m0098417.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 2B88lYQa014701; Thu, 8 Dec 2022 08:47:34 GMT Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3mbcqjg095-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Dec 2022 08:47:34 +0000 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 2B7HHVO3027321; Thu, 8 Dec 2022 08:47:32 GMT Received: from smtprelay03.fra02v.mail.ibm.com ([9.218.2.224]) by ppma04ams.nl.ibm.com (PPS) with ESMTPS id 3m9ks444st-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 08 Dec 2022 08:47:32 +0000 Received: from smtpav01.fra02v.mail.ibm.com (smtpav01.fra02v.mail.ibm.com [10.20.54.100]) by smtprelay03.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 2B88lSpI42926560 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 8 Dec 2022 08:47:28 GMT Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8FD9520043; Thu, 8 Dec 2022 08:47:28 +0000 (GMT) Received: from smtpav01.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4994E20040; Thu, 8 Dec 2022 08:47:26 +0000 (GMT) Received: from [9.197.235.114] (unknown [9.197.235.114]) by smtpav01.fra02v.mail.ibm.com (Postfix) with ESMTP; Thu, 8 Dec 2022 08:47:25 +0000 (GMT) Message-ID: Date: Thu, 8 Dec 2022 16:47:24 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v5, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions Content-Language: en-US To: HAO CHEN GUI Cc: Segher Boessenkool , David , Peter Bergner , gcc-patches References: From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: __rb5ZGG12bKesxJM4jr9vSU1gJ5Svox X-Proofpoint-ORIG-GUID: cHK-UV5klqI3K9Xj5pX2Ohv6HDvq7p10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.923,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-12-08_04,2022-12-07_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 adultscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2212080070 X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Haochen, Thanks for the update, some comments are inlined as below. on 2022/12/2 15:03, HAO CHEN GUI wrote: > Hi, > For scalar extract/insert instructions, exponent field can be stored in a > 32-bit register. So this patch changes the mode of exponent field from DI to > SI so that these instructions can be generated in a 32-bit environment. Also > it removes TARGET_64BIT check for these instructions. > > The instructions using DI registers can be invoked with -mpowerpc64 in a > 32-bit environment. The patch changes insn condition from TARGET_64BIT to > TARGET_POWERPC64 for those instructions. > > This patch also changes prototypes and catagories of relevant built-ins and ~~~~~ categories > effective target checks of test cases. > > Compared to last version, main changes are to remove 64-bit environment > requirement for relevant built-ins in extend.texi. And to change the type of > arguments of relevant built-ins in rs6000-overload.def. > > Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. > Is this okay for trunk? Any recommendations? Thanks a lot. > > ChangeLog > 2022-12-01 Haochen Gui > > gcc/ > * config/rs6000/rs6000-builtins.def > (__builtin_vsx_scalar_extract_exp): Set return type to const unsigned > int and move it from power9-64 to power9 catatlog. ~~~~~~~ catalog > (__builtin_vsx_scalar_extract_sig): Set return type to const unsigned > long long. > (__builtin_vsx_scalar_insert_exp): Set type of second argument to > unsigned int. > (__builtin_vsx_scalar_insert_exp_dp): Set type of second argument to > unsigned int and move it from power9-64 to power9 catatlog. ~~~~~~~ > * config/rs6000/vsx.md (xsxexpdp): Set mode of first operand to > SImode. Remove TARGET_64BIT from insn condition. > (xsxsigdp): Change insn condition from TARGET_64BIT to TARGET_POWERPC64. > (xsiexpdp): Change insn condition from TARGET_64BIT to > TARGET_POWERPC64. Set mode of third operand to SImode. > (xsiexpdpf): Set mode of third operand to SImode. Remove TARGET_64BIT > from insn condition. > * config/rs6000/rs6000-overload.def > (__builtin_vec_scalar_insert_exp): Set type of second argument to > unsigned int. > * doc/extend.texi (scalar_insert_exp): Set type of second argument to > unsigned int and remove 64-bit environment requirement when > significand has a float type. > (scalar_extract_exp): Remove 64-bit environment requirement. > > gcc/testsuite/ > * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Remove lp64 check. > * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Remove lp64 check. > * gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Deleted as the case is > invalid now. > * gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Replace lp64 check > with has_arch_ppc64. > * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Likewise. > * gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check > with has_arch_ppc64. Set type of exponent to unsigned int. > * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Set type of exponent > to unsigned int. > * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Replace lp64 check > with has_arch_ppc64. Set type of exponent to unsigned int. > * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Remove lp64 check. > Set type of exponent to unsigned int. > * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Set type of exponent to > unsigned int. > * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Remove lp64 check. Set > type of exponent to unsigned int. > * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise. > * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Deleted as the case is > invalid now. > > patch.diff > diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def > index f76f54793d7..d8d67fa0cad 100644 > --- a/gcc/config/rs6000/rs6000-builtins.def > +++ b/gcc/config/rs6000/rs6000-builtins.def > @@ -2833,6 +2833,11 @@ > const signed int __builtin_dtstsfi_ov_td (const int<6>, _Decimal128); > TSTSFI_OV_TD dfptstsfi_unordered_td {} > > + const unsigned int __builtin_vsx_scalar_extract_exp (double); > + VSEEDP xsxexpdp {} > + > + const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned int); > + VSIEDPF xsiexpdpf {} This __builtin_vsx_scalar_insert_exp_dp still requires 64-bit, see further explanation below ... > > [power9-64] > void __builtin_altivec_xst_len_r (vsc, void *, long); > @@ -2847,19 +2852,13 @@ > pure vsc __builtin_vsx_lxvl (const void *, signed long); > LXVL lxvl {} > > - const signed long __builtin_vsx_scalar_extract_exp (double); > - VSEEDP xsxexpdp {} > - > - const signed long __builtin_vsx_scalar_extract_sig (double); > + const unsigned long long __builtin_vsx_scalar_extract_sig (double); > VSESDP xsxsigdp {} > > const double __builtin_vsx_scalar_insert_exp (unsigned long long, \ > - unsigned long long); > + unsigned int); > VSIEDP xsiexpdp {} > > - const double __builtin_vsx_scalar_insert_exp_dp (double, unsigned long long); > - VSIEDPF xsiexpdpf {} > - > pure vsc __builtin_vsx_xl_len_r (void *, signed long); > XL_LEN_R xl_len_r {} > > diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def > index 44e2945aaa0..8220d85271f 100644 > --- a/gcc/config/rs6000/rs6000-overload.def > +++ b/gcc/config/rs6000/rs6000-overload.def > @@ -4507,9 +4507,9 @@ > VSESQP > > [VEC_VSIE, scalar_insert_exp, __builtin_vec_scalar_insert_exp] > - double __builtin_vec_scalar_insert_exp (unsigned long long, unsigned long long); > + double __builtin_vec_scalar_insert_exp (unsigned long long, unsigned int); > VSIEDP > - double __builtin_vec_scalar_insert_exp (double, unsigned long long); > + double __builtin_vec_scalar_insert_exp (double, unsigned int); > VSIEDPF > _Float128 __builtin_vec_scalar_insert_exp (unsigned __int128, unsigned long long); > VSIEQP > diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md > index e226a93bbe5..9d3a2340a79 100644 > --- a/gcc/config/rs6000/vsx.md > +++ b/gcc/config/rs6000/vsx.md > @@ -5095,10 +5095,10 @@ (define_insn "xsxexpqp_" > > ;; VSX Scalar Extract Exponent Double-Precision > (define_insn "xsxexpdp" > - [(set (match_operand:DI 0 "register_operand" "=r") > - (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] > + [(set (match_operand:SI 0 "register_operand" "=r") > + (unspec:SI [(match_operand:DF 1 "vsx_register_operand" "wa")] > UNSPEC_VSX_SXEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR" > "xsxexpdp %0,%x1" > [(set_attr "type" "integer")]) > > @@ -5116,7 +5116,7 @@ (define_insn "xsxsigdp" > [(set (match_operand:DI 0 "register_operand" "=r") > (unspec:DI [(match_operand:DF 1 "vsx_register_operand" "wa")] > UNSPEC_VSX_SXSIG))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR && TARGET_POWERPC64" > "xsxsigdp %0,%x1" > [(set_attr "type" "integer")]) > > @@ -5145,9 +5145,9 @@ (define_insn "xsiexpqp_" > (define_insn "xsiexpdp" > [(set (match_operand:DF 0 "vsx_register_operand" "=wa") > (unspec:DF [(match_operand:DI 1 "register_operand" "r") > - (match_operand:DI 2 "register_operand" "r")] > + (match_operand:SI 2 "register_operand" "r")] > UNSPEC_VSX_SIEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR && TARGET_POWERPC64" > "xsiexpdp %x0,%1,%2" > [(set_attr "type" "fpsimple")]) > > @@ -5155,9 +5155,9 @@ (define_insn "xsiexpdp" > (define_insn "xsiexpdpf" > [(set (match_operand:DF 0 "vsx_register_operand" "=wa") > (unspec:DF [(match_operand:DF 1 "register_operand" "r") > - (match_operand:DI 2 "register_operand" "r")] > + (match_operand:SI 2 "register_operand" "r")] > UNSPEC_VSX_SIEXPDP))] > - "TARGET_P9_VECTOR && TARGET_64BIT" > + "TARGET_P9_VECTOR" > "xsiexpdp %x0,%1,%2" > [(set_attr "type" "fpsimple")]) ... the final instruction xsiexpdp, as its description: src1 <- GPR[RA] // operand 1, src2 <- GPR[RB] VSR[32×TX+T].dword[0].bit[0] <- src1.bit[0] VSR[32×TX+T].dword[0].bit[1:11] <- src2.bit[53:63] VSR[32×TX+T].dword[0].bit[12:63] <- src1.bit[12:63] // it requires src1 should be 64 bits VSR[32×TX+T].dword[1] <- 0x0000_0000_0000_0000 Without TARGET_POWERPC64, we have to put the operand 1 into two separated GPRs, but only one GPR used by this instruction, the final result would be wrong. > > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 7fe7f8817cd..cdadcfeb40e 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -19552,8 +19552,8 @@ unsigned long long int scalar_extract_sig (double source); > unsigned __int128 scalar_extract_sig (__ieee128 source); > > double scalar_insert_exp (unsigned long long int significand, > - unsigned long long int exponent); > -double scalar_insert_exp (double significand, unsigned long long int exponent); > + unsigned int exponent); > +double scalar_insert_exp (double significand, unsigned int exponent); > > ieee_128 scalar_insert_exp (unsigned __int128 significand, > unsigned long long int exponent); > @@ -19573,7 +19573,9 @@ bool scalar_test_neg (double source); > bool scalar_test_neg (__ieee128 source); > @end smallexample > > -The @code{scalar_extract_exp} and @code{scalar_extract_sig} > +The @code{scalar_extract_exp} > +functions require an environment supporting ISA 3.0 or later. This change looks wrong, as the @code{scalar_extract_exp} functions in the context include both functions below: unsigned int scalar_extract_exp (double source); unsigned long long int scalar_extract_exp (__ieee128 source); The former doesn't requires 64-bit but the latter still requires (since IEEE128_HW requires 64-bit). So how about something like: "The @code{scalar_extract_exp} function with 64-bit source argument require an environment supporting ISA 3.0 or later. The @code{scalar_extract_exp} with 128-bit source argument and @code{scalar_extract_sig} functions require a 64-bit environment supporting ISA 3.0 or later. " This documentation update reminds me of that the current prototype of __ieee128 variant can be: unsigned int scalar_extract_exp (__ieee128 source); type unsigned int is enough for the exponent. It means xsxexpqp_ can also use SImode rather than DImode. > +The @code{scalar_extract_sig} > functions require a 64-bit environment supporting ISA 3.0 or later. > The @code{scalar_extract_exp} and @code{scalar_extract_sig} built-in > functions return the significand and the biased exponent value > @@ -19591,8 +19593,10 @@ returned from the @code{scalar_extract_sig} function. Use the > @code{scalar_test_neg} function to test the sign of its @code{double} > argument. > > -The @code{scalar_insert_exp} > +The @code{scalar_insert_exp} with an integer @code{significand} > functions require a 64-bit environment supporting ISA 3.0 or later. > +The @code{scalar_insert_exp} with a float @code{significand} > +functions require an environment supporting ISA 3.0 or later. > When supplied with a 64-bit first argument, the > @code{scalar_insert_exp} built-in function returns a double-precision > floating point value that is constructed by assembling the values of its > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > index 35bf1b240f3..a97a2b6ec98 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-0.c > @@ -1,9 +1,7 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ I noticed that some of updated test cases remove "{ target { powerpc*-*-* } } " from dg-do, but some don't (like closely following scalar-extract-exp-1.c). IMHO, we should keep consistent here, in this bucket we still have other scalar-* untouched, I prefer to keep it unchanged. Sorry that I didn't catch this in the previous review. > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > -/* This test should succeed only on 64-bit configurations. */ > #include > > unsigned int > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c > index 9737762c1d4..1cb438f9b70 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-1.c > @@ -1,9 +1,7 @@ > /* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > /* { dg-require-effective-target powerpc_p9vector_ok } */ > /* { dg-options "-mdejagnu-cpu=power8" } */ > > -/* This test should succeed only on 64-bit configurations. */ > #include > > unsigned int > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c > deleted file mode 100644 > index 53b67c95cf9..00000000000 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-2.c > +++ /dev/null > @@ -1,20 +0,0 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target ilp32 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > -/* { dg-options "-mdejagnu-cpu=power9" } */ > - > -/* This test only runs on 32-bit configurations, where a compiler error > - should be issued because this builtin is not available on > - 32-bit configurations. */ > - > -#include > - > -unsigned int > -get_exponent (double *p) > -{ > - double source = *p; > - > - return scalar_extract_exp (source); /* { dg-error "'__builtin_vsx_scalar_extract_exp' requires the" } */ > -} > - > - > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > index b9dd7d61aae..136471a35b3 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-exp-6.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ It gets rid of 64-bit env, why do we need has_arch_ppc64 here? ... > +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ ... the comment is wrong if has_arch_ppc64 is not intentional. > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c > index 637080652b7..3be7eb13566 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-0.c > @@ -1,7 +1,7 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > /* This test should succeed only on 64-bit configurations. */ > #include Missing to update scalar-extract-sig-1.c? It should use "has_arch_ppc64" instead. > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c > index c85072da138..b96a745157d 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-extract-sig-6.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c > index d8243258a67..7e70d6e2642 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-0.c > @@ -1,17 +1,17 @@ > -/* { dg-do compile { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target powerpc_p9vector_ok } */ > +/* { dg-do compile } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target powerpc_p9vector_ok } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > > double > insert_exponent (unsigned long long int *significand_p, > - unsigned long long int *exponent_p) > + unsigned int *exponent_p) > { > unsigned long long int significand = *significand_p; > - unsigned long long int exponent = *exponent_p; > + unsigned int exponent = *exponent_p; > > return scalar_insert_exp (significand, exponent); > } > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c > index 8260b107178..a7297319bc4 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-1.c > @@ -8,10 +8,10 @@ > > double > insert_exponent (unsigned long long int *significand_p, > - unsigned long long int *exponent_p) > + unsigned int *exponent_p) > { > unsigned long long int significand = *significand_p; > - unsigned long long int exponent = *exponent_p; > + unsigned int exponent = *exponent_p; > > return __builtin_vec_scalar_insert_exp (significand, exponent); /* { dg-error "'__builtin_vsx_scalar_insert_exp' requires" } */ > } > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c > index 384fc9cc675..343620fbe17 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-12.c > @@ -1,7 +1,7 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target has_arch_ppc64 } */ > +/* { dg-require-effective-target p9vector_hw } */ > > /* This test should succeed only on 64-bit configurations. */ > #include > @@ -9,10 +9,10 @@ > > double > insert_exponent (unsigned long long int *significand_p, > - unsigned long long int *exponent_p) > + unsigned int *exponent_p) > { > unsigned long long int significand = *significand_p; > - unsigned long long int exponent = *exponent_p; > + unsigned int exponent = *exponent_p; > > return scalar_insert_exp (significand, exponent); > } > @@ -24,8 +24,8 @@ main () > { > unsigned long long int significand_1 = 0x18000000000000LL; > unsigned long long int significand_2 = 0x1a000000000000LL; > - unsigned long long int exponent_1 = 62 + BIAS_FOR_DOUBLE_EXP; > - unsigned long long int exponent_2 = 49 + BIAS_FOR_DOUBLE_EXP; > + unsigned int exponent_1 = 62 + BIAS_FOR_DOUBLE_EXP; > + unsigned int exponent_2 = 49 + BIAS_FOR_DOUBLE_EXP; > > double x = (double) (0x1800ULL << 50); > double z = (double) (0x1a00ULL << 37); > diff --git a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c > index 0e004224277..6c3b1ccd523 100644 > --- a/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c > +++ b/gcc/testsuite/gcc.target/powerpc/bfp/scalar-insert-exp-13.c > @@ -1,18 +1,16 @@ > -/* { dg-do run { target { powerpc*-*-* } } } */ > -/* { dg-require-effective-target lp64 } */ > -/* { dg-require-effective-target p9vector_hw } */ > +/* { dg-do run } */ > /* { dg-options "-mdejagnu-cpu=power9" } */ > +/* { dg-require-effective-target p9vector_hw } */ As the comment above, this scalar_insert_exp variant needs has_arch_ppc64, the others need to be updated accordingly. BR, Kewen