From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by sourceware.org (Postfix) with ESMTPS id BF4763858D1E for ; Fri, 28 Jul 2023 02:55:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BF4763858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=starfivetech.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=starfivetech.com Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id AA10724E277; Fri, 28 Jul 2023 10:55:39 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 28 Jul 2023 10:55:39 +0800 Received: from [192.168.125.202] (113.72.147.196) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 28 Jul 2023 10:55:38 +0800 Message-ID: Date: Fri, 28 Jul 2023 10:55:38 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] RISC-V: Fix uninitialized and redundant use of which_alternative Content-Language: en-US To: Patrick O'Neill , Kito Cheng , "juzhe.zhong@rivai.ai" CC: gcc-patches References: <20230727094859.3884298-1-demin.han@starfivetech.com> <4F1CE7168EFB3E1A+2023072718223714228879@rivai.ai> From: Demin Han In-Reply-To: Content-Type: text/plain; charset="UTF-8" X-Originating-IP: [113.72.147.196] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00,BODY_8BITS,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Sorry for not consider rv32 config. The fix is OK. If convenient, please commit it. On 2023/7/28 4:46, Patrick O'Neill wrote: > The newly added testcase fails on rv32 targets with this message: > FAIL: gcc.target/riscv/rvv/autovec/madd-split2-1.c -O3 -ftree-vectorize= (test for excess errors) >=20 > verbose log: > compiler exited with status 1 > output is: > cc1: error: ABI requires '-march=3Drv32' >=20 > Something like this appears to fix the issue: >=20 > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > index 14a9802667e..e10a9e9d0f5 100644 > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c > @@ -1,5 +1,5 @@ > =C2=A0/* { dg-do compile } */ > -/* { dg-options "-march=3Drv64gcv_zvl256b -O3 -fno-cprop-registers -fn= o-dce --param riscv-autovec-preference=3Dscalable" } */ > +/* { dg-options "-march=3Drv64gcv_zvl256b -mabi=3Dlp64d -O3 > -fno-cprop-registers -fno-dce --param riscv-autovec-preference=3Dscalab= le" > =C2=A0} */ > =C2=A0 > =C2=A0long > =C2=A0foo (long *__restrict a, long *__restrict b, long n) >=20 > On 7/27/23 04:57, Kito Cheng via Gcc-patches wrote: >=20 >> My first impression is those emit_insn (gen_rtx_SET()) seems >> necessary, but I got the point after I checked vector.md :P >> >> Committed to trunk, thanks :) >> >> >> On Thu, Jul 27, 2023 at 6:23=E2=80=AFPMjuzhe.zhong@rivai.ai >> =C2=A0 wrote: >>> Oh, YES. >>> >>> Thanks for fixing it. It makes sense since the ternary operations in = "vector.md" >>> generate "vmv.v.v" according to RA. >>> >>> Thanks for fixing it. >>> >>> @kito: Could you confirm it? If it's ok to you, commit it for Han (I = am lazy to commit patches :). >>> >>> >>> >>> juzhe.zhong@rivai.ai >>> >>> From: demin.han >>> Date: 2023-07-27 17:48 >>> To:gcc-patches@gcc.gnu.org >>> CC:kito.cheng@gmail.com;juzhe.zhong@rivai.ai >>> Subject: [PATCH] RISC-V: Fix uninitialized and redundant use of which= _alternative >>> When pass split2 starts, which_alternative is random depending on >>> last set of certain pass. >>> >>> Even initialized, the generated movement is redundant. >>> The movement can be generated by assembly output template. >>> >>> Signed-off-by: demin.han >>> >>> gcc/ChangeLog: >>> >>> * config/riscv/autovec.md: Delete which_alternative use in split >>> >>> gcc/testsuite/ChangeLog: >>> >>> * gcc.target/riscv/rvv/autovec/madd-split2-1.c: New test. >>> >>> --- >>> gcc/config/riscv/autovec.md=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 | 12 ------------ >>> .../gcc.target/riscv/rvv/autovec/madd-split2-1.c=C2=A0=C2=A0=C2=A0 | = 13 +++++++++++++ >>> 2 files changed, 13 insertions(+), 12 deletions(-) >>> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-sp= lit2-1.c >>> >>> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.m= d >>> index d899922586a..b7ea3101f5a 100644 >>> --- a/gcc/config/riscv/autovec.md >>> +++ b/gcc/config/riscv/autovec.md >>> @@ -1012,8 +1012,6 @@ (define_insn_and_split "*fma" >>> =C2=A0=C2=A0=C2=A0 [(const_int 0)] >>> =C2=A0=C2=A0=C2=A0 { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> -=C2=A0=C2=A0=C2=A0 if (which_alternative =3D=3D 2) >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_insn (gen_rtx_SET (operands[0], = operands[3])); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx ops[] =3D {operands[0], operands[1= ], operands[2], operands[3], operands[0]}; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_ternary_insn = (code_for_pred_mul_plus (mode), >>> =C2=A0=C2=A0=C2=A0 riscv_vector::RVV_TERNOP, ops, operands[4]); >>> @@ -1058,8 +1056,6 @@ (define_insn_and_split "*fnma" >>> =C2=A0=C2=A0=C2=A0 [(const_int 0)] >>> =C2=A0=C2=A0=C2=A0 { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> -=C2=A0=C2=A0=C2=A0 if (which_alternative =3D=3D 2) >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_insn (gen_rtx_SET (operands[0], = operands[3])); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx ops[] =3D {operands[0], operands[1= ], operands[2], operands[3], operands[0]}; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_ternary_insn = (code_for_pred_minus_mul (mode), >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::RVV_TE= RNOP, ops, operands[4]); >>> @@ -1102,8 +1098,6 @@ (define_insn_and_split "*fma" >>> =C2=A0=C2=A0=C2=A0 [(const_int 0)] >>> =C2=A0=C2=A0=C2=A0 { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> -=C2=A0=C2=A0=C2=A0 if (which_alternative =3D=3D 2) >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_insn (gen_rtx_SET (operands[0], = operands[3])); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx ops[] =3D {operands[0], operands[1= ], operands[2], operands[3], operands[0]}; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_fp_ternary_in= sn (code_for_pred_mul (PLUS, mode), >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::RVV_TERNOP, ops, o= perands[4]); >>> @@ -1148,8 +1142,6 @@ (define_insn_and_split "*fnma" >>> =C2=A0=C2=A0=C2=A0 [(const_int 0)] >>> =C2=A0=C2=A0=C2=A0 { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> -=C2=A0=C2=A0=C2=A0 if (which_alternative =3D=3D 2) >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_insn (gen_rtx_SET (operands[0], = operands[3])); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx ops[] =3D {operands[0], operands[1= ], operands[2], operands[3], operands[0]}; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_fp_ternary_in= sn (code_for_pred_mul_neg (PLUS, mode), >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::RVV_TERNOP, ops, o= perands[4]); >>> @@ -1194,8 +1186,6 @@ (define_insn_and_split "*fms" >>> =C2=A0=C2=A0=C2=A0 [(const_int 0)] >>> =C2=A0=C2=A0=C2=A0 { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> -=C2=A0=C2=A0=C2=A0 if (which_alternative =3D=3D 2) >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_insn (gen_rtx_SET (operands[0], = operands[3])); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx ops[] =3D {operands[0], operands[1= ], operands[2], operands[3], operands[0]}; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_fp_ternary_in= sn (code_for_pred_mul (MINUS, mode), >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::RVV_TERNOP, ops, o= perands[4]); >>> @@ -1242,8 +1232,6 @@ (define_insn_and_split "*fnms" >>> =C2=A0=C2=A0=C2=A0 [(const_int 0)] >>> =C2=A0=C2=A0=C2=A0 { >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_vsetvl (mode, operands[4]); >>> -=C2=A0=C2=A0=C2=A0 if (which_alternative =3D=3D 2) >>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 emit_insn (gen_rtx_SET (operands[0], = operands[3])); >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtx ops[] =3D {operands[0], operands[1= ], operands[2], operands[3], operands[0]}; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::emit_vlmax_fp_ternary_in= sn (code_for_pred_mul_neg (MINUS, mode), >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 riscv_vector::RVV_TERNOP, ops, o= perands[4]); >>> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1= .c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >>> new file mode 100644 >>> index 00000000000..14a9802667e >>> --- /dev/null >>> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c >>> @@ -0,0 +1,13 @@ >>> +/* { dg-do compile } */ >>> +/* { dg-options "-march=3Drv64gcv_zvl256b -O3 -fno-cprop-registers -= fno-dce --param riscv-autovec-preference=3Dscalable" } */ >>> + >>> +long >>> +foo (long *__restrict a, long *__restrict b, long n) >>> +{ >>> +=C2=A0 long i; >>> +=C2=A0 for (i =3D 0; i < n; ++i) >>> +=C2=A0=C2=A0=C2=A0 a[i] =3D b[i] + i * 8; >>> +=C2=A0 return a[1]; >>> +} >>> + >>> +/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */ >>> --=20 >>> 2.41.0 >>> >>>