From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 129099 invoked by alias); 17 Sep 2019 11:17:33 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 129091 invoked by uid 89); 17 Sep 2019 11:17:33 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-12.9 required=5.0 tests=AWL,BAYES_00,KAM_NUMSUBJECT,SPF_HELO_PASS,SPF_PASS autolearn=no version=3.3.1 spammy=HX-Spam-Relays-External:!127.0.0.1!, H*RU:!127.0.0.1!, 1794, HX-Languages-Length:2188 X-HELO: huawei.com Received: from szxga07-in.huawei.com (HELO huawei.com) (45.249.212.35) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 17 Sep 2019 11:17:31 +0000 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 4C0B4EFCB33159F43CDB; Tue, 17 Sep 2019 19:17:26 +0800 (CST) Received: from [127.0.0.1] (10.74.221.148) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Tue, 17 Sep 2019 19:17:19 +0800 To: CC: "Richard Earnshaw (lists)" , James Greenhalgh , , , , "Tangnianyao (ICT)" From: Shaokun Zhang Subject: [Question on aarch64] Questions on TLB range instructions on aarch64 Message-ID: Date: Tue, 17 Sep 2019 11:17:00 -0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-IsSubscribed: yes X-SW-Source: 2019-09/txt/msg00993.txt.bz2 Hi aarch64 maintainers, Sorry to noise you again. We(HiSilicon) next generation CPU core will support "ARMv8.4-TLBI, TLB maintenance and TLB range instructions" feature, so I try to compile it that tlbi rvae1is is replaced in linux kernel which is in my local branch, there are some error messages: /tmp/ccD5TFDe.s: Assembler messages: /tmp/ccD5TFDe.s:991: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:1012: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:1794: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:1815: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:2398: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:2419: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:3155: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:3176: Error: unknown or missing operation name at operand 1 -- `tlbi rvae1is,x0' /tmp/ccD5TFDe.s:1016: Error: attempt to move .org backwards /tmp/ccD5TFDe.s:1819: Error: attempt to move .org backwards /tmp/ccD5TFDe.s:2423: Error: attempt to move .org backwards /tmp/ccD5TFDe.s:3180: Error: attempt to move .org backwards make[2]: *** [arch/arm64/mm/hugetlbpage.o] Error 1 make[1]: *** [arch/arm64/mm] Error 2 make: *** [sub-make] Error 2 GCC version is as follow: gcc (GCC) 9.2.0 Copyright (C) 2019 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. It seems that GCC doesn't support this new instruction and I checked that LLVM has already supported this instruction, https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AArch64/AArch64SystemOperands.td So my question is that does GCC have the plan to support this instruction recently? If not, can you give me some suggestion to do it? I'm not the expert on it ;-) Thanks in advance, Shaokun