* [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions.
@ 2019-05-29 14:48 Srinath Parvathaneni
2019-07-23 15:34 ` Srinath Parvathaneni
2019-07-30 14:00 ` Richard Earnshaw (lists)
0 siblings, 2 replies; 3+ messages in thread
From: Srinath Parvathaneni @ 2019-05-29 14:48 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, Richard Earnshaw, Ramana Radhakrishnan, Kyrylo Tkachov
[-- Attachment #1: Type: text/plain, Size: 2376 bytes --]
Hello,
The initial implementation of the FP16 extension added HFmode support to
a limited number of the standard names. Following
https://gcc.gnu.org/ml/gcc-patches/2016-08/msg00168.html , this patch
extends the HFmode support to the names implemented by the ARM
<vrint_pattern> and l<vrint_pattern> expanders: btrunc, ceil, round,
floor, nearbyint and rint. This patch also changes the patterns
supporting the neon_vrnd* and neon_vcvt* Adv.SIMD intrinsics to use the
standard names, where apropriate.
No new tests are added. The ARM tests for the SF and DF mode variants of
these names are based on GCC builtin functions and there doesn't seem to
be an obvious alternative to trigger the new patterns through the
standard names. The pattern definitions though are tested through the
Adv.SIMD intrinsics.
The following patch reworks the implementation for HFmode VRINT to
remove a number of redundant constructs that were added in the initial
implementation.
The two patches have been tested for arm-none-linux-gnueabihf with
native bootstrap and make check and for arm-none-eabi with
cross-compiled check-gcc on an ARMv8.4-A emulator.
Ok for trunk? If ok, could someone please commit the patch on my behalf,
I don't have commit rights.
2019-05-29 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
Matthew Wahab <matthew.wahab@arm.com>
* config/arm/iterators.md (fp16_rnd_str): Replace UNSPEC_VRND
values with equivalent UNSPEC_VRINT values. Add UNSPEC_NVRINTZ,
UNSPEC_NVRINTA, UNSPEC_NVRINTM, UNSPEC_NVRINTN, UNSPEC_NVRINTP,
UNSPEC_NVRINTX.
(vrint_variant): Fix some white-space.
(vrint_predicable): Fix some white-space.
* config/arm/neon.md (neon_v<fp16_rnd_str><mode>): Replace
FP16_RND iterator with NEON_VRINT and update the rest of the
pattern accordingly.
(neon_vcvt<vcvth_op><sup><mode>): Replace with
neon_vcvt<nvrint_variant><su><mode>.
(neon_vcvt<nvrint_variant><su><mode>): New.
(neon_vcvtn<su><mode>): New.
* config/arm/unspecs.md: Add UNSPEC_VRINTN.
* config/arm/vfp.md (neon_v<fp16_rnd_str>hf): Convert to an
expander invoking <vrint_pattern>hf2.
(neon_vrndihf): Remove.
(neon_vrndnhf): New.
(neon_vcvt<vcvth_op>h<sup>si): Remove.
(<vrint_pattern>hf2): New.
(l<vrint_pattern><su_optab>hfsi2): New.
(neon_vcvt<vrint_variant>h<su>si): New.
(neon_vcvtnh<su>si): New.
[-- Attachment #2: rb10543.patch --]
[-- Type: application/octet-stream, Size: 7808 bytes --]
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index eb07c5b90c1b1905d35d7b480bdbe7d7a45ab7ba..13455d4d06df80cfe5b855b45f2607262fd233df 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -881,9 +881,12 @@
(UNSPEC_VCVTP_S "p") (UNSPEC_VCVTP_U "p")])
(define_int_attr fp16_rnd_str
- [(UNSPEC_VRND "rnd") (UNSPEC_VRNDA "rnda")
- (UNSPEC_VRNDM "rndm") (UNSPEC_VRNDN "rndn")
- (UNSPEC_VRNDP "rndp") (UNSPEC_VRNDX "rndx")])
+ [(UNSPEC_VRINTZ "rnd") (UNSPEC_VRINTA "rnda")
+ (UNSPEC_VRINTM "rndm") (UNSPEC_VRINTP "rndp")
+ (UNSPEC_VRINTR "rndi") (UNSPEC_VRINTX "rndx")
+ (UNSPEC_NVRINTZ "rnd") (UNSPEC_NVRINTA "rnda")
+ (UNSPEC_NVRINTM "rndm") (UNSPEC_NVRINTN "rndn")
+ (UNSPEC_NVRINTP "rndp") (UNSPEC_NVRINTX "rndx")])
(define_int_attr fp16_rnd_insn
[(UNSPEC_VRND "vrintz") (UNSPEC_VRNDA "vrinta")
@@ -941,13 +944,13 @@
;; Suffixes for vrint instructions specifying rounding modes.
(define_int_attr vrint_variant [(UNSPEC_VRINTZ "z") (UNSPEC_VRINTP "p")
- (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
- (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
+ (UNSPEC_VRINTA "a") (UNSPEC_VRINTM "m")
+ (UNSPEC_VRINTR "r") (UNSPEC_VRINTX "x")])
;; Some of the vrint instuctions are predicable.
(define_int_attr vrint_predicable [(UNSPEC_VRINTZ "yes") (UNSPEC_VRINTP "no")
- (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
- (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
+ (UNSPEC_VRINTA "no") (UNSPEC_VRINTM "no")
+ (UNSPEC_VRINTR "yes") (UNSPEC_VRINTX "yes")])
(define_int_attr vrint_conds [(UNSPEC_VRINTZ "nocond") (UNSPEC_VRINTP "unconditional")
(UNSPEC_VRINTA "unconditional") (UNSPEC_VRINTM "unconditional")
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 726b7281a11be92d0b7a91fa7b8ba9efd1b68ac9..75066c3f3d3cacc59457b11b9f2891cbabe84267 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1002,9 +1002,9 @@
[(set (match_operand:VH 0 "s_register_operand" "=w")
(unspec:VH
[(match_operand:VH 1 "s_register_operand" "w")]
- FP16_RND))]
+ NEON_VRINT))]
"TARGET_NEON_FP16INST"
- "<fp16_rnd_insn>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
+ "vrint<nvrint_variant>.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
[(set_attr "type" "neon_fp_round_s<q>")]
)
@@ -4307,14 +4307,23 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_int_to_fp_<VH_elem_ch><q>")]
)
-(define_insn "neon_vcvt<vcvth_op><sup><mode>"
+(define_insn "neon_vcvt<nvrint_variant><su><mode>"
[(set
(match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
- (unspec:<VH_CVTTO>
- [(match_operand:VH 1 "s_register_operand" "w")]
- VCVT_HF_US))]
+ (FIXUORS:<VH_CVTTO>
+ (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")] NEON_VCVT)))]
+ "TARGET_NEON_FP16INST"
+ "vcvt<nvrint_variant>.<su>%#16.f16\t%<V_reg>0, %<V_reg>1"
+ [(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
+)
+
+(define_insn "neon_vcvtn<su><mode>"
+ [(set
+ (match_operand:<VH_CVTTO> 0 "s_register_operand" "=w")
+ (FIXUORS:<VH_CVTTO>
+ (unspec:VH [(match_operand:VH 1 "s_register_operand" "w")] UNSPEC_VRINTN)))]
"TARGET_NEON_FP16INST"
- "vcvt<vcvth_op>.<sup>%#16.f16\t%<V_reg>0, %<V_reg>1"
+ "vcvtn.<su>%#16.f16\t%<V_reg>0, %<V_reg>1"
[(set_attr "type" "neon_fp_to_int_<VH_elem_ch><q>")]
)
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index 174bcc5e3d5e1123cb1c1a595f5003884840aea8..41d0d431453d9515ecee5e3e7d07b00bfd1ae33f 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -83,6 +83,8 @@
; FPSCR rounding mode and signal inexactness.
UNSPEC_VRINTA ; Represent a float to integral float rounding
; towards nearest, ties away from zero.
+ UNSPEC_VRINTN ; Represent a float to integral float rounding
+ ; towards nearest.
UNSPEC_PROBE_STACK ; Probe stack memory reference
UNSPEC_NONSECURE_MEM ; Represent non-secure memory in ARMv8-M with
; security extension
diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index e0aaa7b00bb41c046da4531a293e123c94e8b9a4..3c303da756dcb660b56118bf4748ca987b7a91e0 100644
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -924,26 +924,28 @@
})
;; VRND for FP16.
-(define_insn "neon_v<fp16_rnd_str>hf"
+(define_expand "neon_v<fp16_rnd_str>hf"
[(set (match_operand:HF 0 "s_register_operand" "=w")
(unspec:HF
[(match_operand:HF 1 "s_register_operand" "w")]
- FP16_RND))]
+ VRINT))]
"TARGET_VFP_FP16INST"
- "<fp16_rnd_insn>.f16\t%0, %1"
- [(set_attr "conds" "unconditional")
- (set_attr "type" "neon_fp_round_s")]
-)
+{
+ emit_insn (gen_<vrint_pattern>hf2 (operands[0], operands[1]));
+ DONE;
+})
-(define_insn "neon_vrndihf"
+(define_insn "neon_vrndnhf"
[(set (match_operand:HF 0 "s_register_operand" "=w")
(unspec:HF
[(match_operand:HF 1 "s_register_operand" "w")]
- UNSPEC_VRNDI))]
- "TARGET_VFP_FP16INST"
- "vrintr.f16\t%0, %1"
- [(set_attr "conds" "unconditional")
- (set_attr "type" "neon_fp_round_s")]
+ UNSPEC_VRINTN))]
+ "TARGET_VFP_FP16INST"
+ "vrintn.f16\\t%0, %1"
+ [(set_attr "predicable" "no")
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "f_rints")
+ (set_attr "conds" "unconditional")]
)
;; Arithmetic insns
@@ -1864,18 +1866,6 @@
DONE;
})
-(define_insn "neon_vcvt<vcvth_op>h<sup>si"
- [(set
- (match_operand:SI 0 "s_register_operand" "=w")
- (unspec:SI
- [(match_operand:HF 1 "s_register_operand" "w")]
- VCVT_HF_US))]
- "TARGET_VFP_FP16INST"
- "vcvt<vcvth_op>.<sup>%#32.f16\t%0, %1"
- [(set_attr "conds" "unconditional")
- (set_attr "type" "f_cvtf2i")]
-)
-
;; Store multiple insn used in function prologue.
(define_insn "*push_multi_vfp"
[(match_parallel 2 "multi_register_push"
@@ -1903,6 +1893,18 @@
(set_attr "conds" "<vrint_conds>")]
)
+(define_insn "<vrint_pattern>hf2"
+ [(set (match_operand:HF 0 "register_operand" "=t")
+ (unspec:HF [(match_operand:HF 1 "register_operand" "t")]
+ VRINT))]
+ "TARGET_VFP_FP16INST"
+ "vrint<vrint_variant>.f16\\t%0, %1"
+ [(set_attr "predicable" "no")
+ (set_attr "predicable_short_it" "no")
+ (set_attr "type" "f_rints")
+ (set_attr "conds" "unconditional")]
+)
+
;; Implements the lround, lfloor and lceil optabs.
(define_insn "l<vrint_pattern><su_optab><mode>si2"
[(set (match_operand:SI 0 "register_operand" "=t")
@@ -1915,6 +1917,38 @@
(set_attr "type" "f_cvtf2i")]
)
+(define_insn "l<vrint_pattern><su_optab>hfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=t")
+ (FIXUORS:SI
+ (unspec:HF [(match_operand:HF 1 "register_operand" "t")] VCVT)))]
+ "TARGET_VFP_FP16INST"
+ "vcvt<vrint_variant>.<su>32.f16\\t%0, %1"
+ [(set_attr "predicable" "no")
+ (set_attr "conds" "unconditional")
+ (set_attr "type" "f_cvtf2i")]
+)
+
+(define_expand "neon_vcvt<vrint_variant>h<su>si"
+ [(match_operand:SI 0 "s_register_operand")
+ (FIXUORS:SI
+ (unspec:HF [(match_operand:HF 1 "s_register_operand")] VCVT))]
+ "TARGET_VFP_FP16INST"
+{
+ emit_insn (gen_l<vrint_pattern><su_optab>hfsi2 (operands[0], operands[1]));
+ DONE;
+})
+
+(define_insn "neon_vcvtnh<su>si"
+ [(set
+ (match_operand:SI 0 "s_register_operand" "=w")
+ (FIXUORS:SI
+ (unspec:SI [(match_operand:HF 1 "s_register_operand" "w")]
+ UNSPEC_VRINTN)))]
+ "TARGET_VFP_FP16INST"
+ "vcvtn.<su>%#32.f16\t%0, %1"
+ [(set_attr "conds" "unconditional")
+ (set_attr "type" "f_cvtf2i")])
+
;; MIN_EXPR and MAX_EXPR eventually map to 'smin' and 'smax' in RTL.
;; The 'smax' and 'smin' RTL standard pattern names do not specify which
;; operand will be returned when both operands are zero (i.e. they may not
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions.
2019-05-29 14:48 [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions Srinath Parvathaneni
@ 2019-07-23 15:34 ` Srinath Parvathaneni
2019-07-30 14:00 ` Richard Earnshaw (lists)
1 sibling, 0 replies; 3+ messages in thread
From: Srinath Parvathaneni @ 2019-07-23 15:34 UTC (permalink / raw)
To: gcc-patches; +Cc: nd, Richard Earnshaw, Ramana Radhakrishnan, Kyrylo Tkachov
Hi,
Pinging for review of https://gcc.gnu.org/ml/gcc-patches/2019-05/msg01921.html.
Regards,
SRI.
________________________________
From: gcc-patches-owner@gcc.gnu.org<mailto:gcc-patches-owner@gcc.gnu.org> <gcc-patches-owner@gcc.gnu.org><mailto:gcc-patches-owner@gcc.gnu.org> on behalf of Srinath Parvathaneni <Srinath.Parvathaneni@arm.com><mailto:Srinath.Parvathaneni@arm.com>
Sent: 29 May 2019 15:47:59
To: gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org> <gcc-patches@gcc.gnu.org><mailto:gcc-patches@gcc.gnu.org>
Cc: nd <nd@arm.com><mailto:nd@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com><mailto:Richard.Earnshaw@arm.com>; Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com><mailto:Ramana.Radhakrishnan@arm.com>; Kyrylo Tkachov <Kyrylo.Tkachov@arm.com><mailto:Kyrylo.Tkachov@arm.com>
Subject: [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions.
Hello,
The initial implementation of the FP16 extension added HFmode support to
a limited number of the standard names. Following
https://gcc.gnu.org/ml/gcc-patches/2016-08/msg00168.html , this patch
extends the HFmode support to the names implemented by the ARM
<vrint_pattern> and l<vrint_pattern> expanders: btrunc, ceil, round,
floor, nearbyint and rint. This patch also changes the patterns
supporting the neon_vrnd* and neon_vcvt* Adv.SIMD intrinsics to use the
standard names, where apropriate.
No new tests are added. The ARM tests for the SF and DF mode variants of
these names are based on GCC builtin functions and there doesn't seem to
be an obvious alternative to trigger the new patterns through the
standard names. The pattern definitions though are tested through the
Adv.SIMD intrinsics.
The following patch reworks the implementation for HFmode VRINT to
remove a number of redundant constructs that were added in the initial
implementation.
The two patches have been tested for arm-none-linux-gnueabihf with
native bootstrap and make check and for arm-none-eabi with
cross-compiled check-gcc on an ARMv8.4-A emulator.
Ok for trunk? If ok, could someone please commit the patch on my behalf,
I don't have commit rights.
2019-05-29 Srinath Parvathaneni <srinath.parvathaneni@arm.com><mailto:srinath.parvathaneni@arm.com>
Matthew Wahab <matthew.wahab@arm.com><mailto:matthew.wahab@arm.com>
* config/arm/iterators.md (fp16_rnd_str): Replace UNSPEC_VRND
values with equivalent UNSPEC_VRINT values. Add UNSPEC_NVRINTZ,
UNSPEC_NVRINTA, UNSPEC_NVRINTM, UNSPEC_NVRINTN, UNSPEC_NVRINTP,
UNSPEC_NVRINTX.
(vrint_variant): Fix some white-space.
(vrint_predicable): Fix some white-space.
* config/arm/neon.md (neon_v<fp16_rnd_str><mode>): Replace
FP16_RND iterator with NEON_VRINT and update the rest of the
pattern accordingly.
(neon_vcvt<vcvth_op><sup><mode>): Replace with
neon_vcvt<nvrint_variant><su><mode>.
(neon_vcvt<nvrint_variant><su><mode>): New.
(neon_vcvtn<su><mode>): New.
* config/arm/unspecs.md: Add UNSPEC_VRINTN.
* config/arm/vfp.md (neon_v<fp16_rnd_str>hf): Convert to an
expander invoking <vrint_pattern>hf2.
(neon_vrndihf): Remove.
(neon_vrndnhf): New.
(neon_vcvt<vcvth_op>h<sup>si): Remove.
(<vrint_pattern>hf2): New.
(l<vrint_pattern><su_optab>hfsi2): New.
(neon_vcvt<vrint_variant>h<su>si): New.
(neon_vcvtnh<su>si): New.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions.
2019-05-29 14:48 [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions Srinath Parvathaneni
2019-07-23 15:34 ` Srinath Parvathaneni
@ 2019-07-30 14:00 ` Richard Earnshaw (lists)
1 sibling, 0 replies; 3+ messages in thread
From: Richard Earnshaw (lists) @ 2019-07-30 14:00 UTC (permalink / raw)
To: Srinath Parvathaneni, gcc-patches
Cc: nd, Ramana Radhakrishnan, Kyrylo Tkachov
On 29/05/2019 15:47, Srinath Parvathaneni wrote:
> Hello,
>
> The initial implementation of the FP16 extension added HFmode support to
> a limited number of the standard names. Following
> https://gcc.gnu.org/ml/gcc-patches/2016-08/msg00168.html , this patch
> extends the HFmode support to the names implemented by the ARM
> <vrint_pattern> and l<vrint_pattern> expanders: btrunc, ceil, round,
> floor, nearbyint and rint. This patch also changes the patterns
> supporting the neon_vrnd* and neon_vcvt* Adv.SIMD intrinsics to use the
> standard names, where apropriate.
>
> No new tests are added. The ARM tests for the SF and DF mode variants of
> these names are based on GCC builtin functions and there doesn't seem to
> be an obvious alternative to trigger the new patterns through the
> standard names. The pattern definitions though are tested through the
> Adv.SIMD intrinsics.
>
> The following patch reworks the implementation for HFmode VRINT to
> remove a number of redundant constructs that were added in the initial
> implementation.
>
> The two patches have been tested for arm-none-linux-gnueabihf with
> native bootstrap and make check and for arm-none-eabi with
> cross-compiled check-gcc on an ARMv8.4-A emulator.
>
> Ok for trunk? If ok, could someone please commit the patch on my behalf,
> I don't have commit rights.
>
> 2019-05-29 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
> Matthew Wahab <matthew.wahab@arm.com>
>
> * config/arm/iterators.md (fp16_rnd_str): Replace UNSPEC_VRND
> values with equivalent UNSPEC_VRINT values. Add UNSPEC_NVRINTZ,
> UNSPEC_NVRINTA, UNSPEC_NVRINTM, UNSPEC_NVRINTN, UNSPEC_NVRINTP,
> UNSPEC_NVRINTX.
> (vrint_variant): Fix some white-space.
> (vrint_predicable): Fix some white-space.
> * config/arm/neon.md (neon_v<fp16_rnd_str><mode>): Replace
> FP16_RND iterator with NEON_VRINT and update the rest of the
> pattern accordingly.
> (neon_vcvt<vcvth_op><sup><mode>): Replace with
> neon_vcvt<nvrint_variant><su><mode>.
> (neon_vcvt<nvrint_variant><su><mode>): New.
> (neon_vcvtn<su><mode>): New.
> * config/arm/unspecs.md: Add UNSPEC_VRINTN.
> * config/arm/vfp.md (neon_v<fp16_rnd_str>hf): Convert to an
> expander invoking <vrint_pattern>hf2.
> (neon_vrndihf): Remove.
> (neon_vrndnhf): New.
> (neon_vcvt<vcvth_op>h<sup>si): Remove.
> (<vrint_pattern>hf2): New.
> (l<vrint_pattern><su_optab>hfsi2): New.
> (neon_vcvt<vrint_variant>h<su>si): New.
> (neon_vcvtnh<su>si): New.
>
Picking just one pattern as an example here, why does:
+(define_insn "l<vrint_pattern><su_optab>hfsi2"
+ [(set (match_operand:SI 0 "register_operand" "=t")
+ (FIXUORS:SI
+ (unspec:HF [(match_operand:HF 1 "register_operand" "t")] VCVT)))]
+ "TARGET_VFP_FP16INST"
+ "vcvt<vrint_variant>.<su>32.f16\\t%0, %1"
+ [(set_attr "predicable" "no")
+ (set_attr "conds" "unconditional")
+ (set_attr "type" "f_cvtf2i")]
+)
still need the unspec inside the FIXUORS? If the pattern does what the
FIX says, then it should be safe to do this directly on the register,
without wrapping it first in an UNSPEC.
The other thing I noticed was:
UNSPEC_VRINTA ; Represent a float to integral float rounding
; towards nearest, ties away from zero.
+ UNSPEC_VRINTN ; Represent a float to integral float rounding
+ ; towards nearest.
So we have VRINTA which rounds to nearest, but rounds ties away from
zero, but VRINTN rounds to nearest but doesn't say what happens when
there is a tie (ie a value exactly half-way between two results. The
architecture treats this as ties-to-even, so I think we should say that
here.
R.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-05-29 14:48 [ARM][PATCH 1/2] Support HFmode for standard names implemented with VRINT instructions Srinath Parvathaneni
2019-07-23 15:34 ` Srinath Parvathaneni
2019-07-30 14:00 ` Richard Earnshaw (lists)
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