From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 6BEC4385E004 for ; Mon, 23 Mar 2020 14:11:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 6BEC4385E004 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=Richard.Earnshaw@foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0EA351FB; Mon, 23 Mar 2020 07:11:01 -0700 (PDT) Received: from [192.168.1.19] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 712683F52E; Mon, 23 Mar 2020 07:11:00 -0700 (PDT) Subject: Re: [PING^2][PATCH] Fix documentation of -mpoke-function-name ARM option To: =?UTF-8?Q?J=c3=a9r=c3=a9my_Lefaure?= , Wilco Dijkstra Cc: GCC Patches References: <20200322181506.6gnsg4qoebutxltm@blatinox.fr> From: Richard Earnshaw Message-ID: Date: Mon, 23 Mar 2020 14:10:59 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200322181506.6gnsg4qoebutxltm@blatinox.fr> Content-Type: text/plain; charset=utf-8 Content-Language: en-GB Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=no autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Mar 2020 14:11:02 -0000 On 22/03/2020 18:15, Jérémy Lefaure wrote: > Hi Wilco, > > On Mon, Mar 09, 2020 at 05:53:41PM +0000, Wilco Dijkstra wrote: >> Hi, >> >> There is no single PC offset that is correct given CPUs may use different offsets. > > Isn't it always an offset of 8 in ARM mode and 4 bytes in Thumb mode ? > At least in ARMv7 and in AArch32 state in ARMv8 ? > No, it depends on the architecture version. Prior to ARMv5 it was implementation defined. Some cores would use +12 in Arm state, others +8. > >> GCC may also schedule the instruction that stores the PC. This feature used to >> work on early Arms but is no longer functional or useful today, so the best way >> forward is to remove it altogether. There are many similar options that have >> been deprecated for years. >> > I didn't know that this feature is no longer working. Thank your for the > info. The poke-function-name feature depends on the long-deprecated APCS variant of the procedure call standard (the AAPCS has been the standard for well over 10 years now). I don't think we should be adding (or, now, even trying to fix) features that are dependent on it. We will be moving away from codegen support for this type of frame layout in the not too distant future. R. > > > Thank your for having reviewed my patch, > Jérémy >