[PATCH] testsuite/s390: Fix risbg-ll-3.c f2_cconly test.

[Robin Dapp <rdapp@linux.ibm.com>]

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Hi,

instead of selecting bits 62 to (wraparound) 59 from r2 and inserting 
them into r3, we select bits 60 to 62 from r3 and insert them into r2 
nowadays.  Adjust the test accordingly.

Is this OK?

Regards
  Robin

gcc/testsuite/ChangeLog:

         * gcc.target/s390/risbg-ll-3.c: Change match pattern.

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From ca1a204ff1753f4902bb58668d0ceafcc17d1232 Mon Sep 17 00:00:00 2001
From: Robin Dapp <rdapp@linux.ibm.com>
Date: Tue, 27 Apr 2021 16:17:35 +0200
Subject: [PATCH] testsuite/s390: Fix risbg-ll-3.c f2_cconly test.

Instead of selecting bits 62 to (wraparound) 59 from r2 and inserting them
into r3, we select bits 60 to 62 from r3 and insert them into r2
nowadays.  Adjust the test accordingly.
---
 gcc/testsuite/gcc.target/s390/risbg-ll-3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/s390/risbg-ll-3.c b/gcc/testsuite/gcc.target/s390/risbg-ll-3.c
index 90d37f2c1ce..864b0d6c417 100644
--- a/gcc/testsuite/gcc.target/s390/risbg-ll-3.c
+++ b/gcc/testsuite/gcc.target/s390/risbg-ll-3.c
@@ -37,7 +37,7 @@ i64 f2 (i64 v_a, i64 v_b)
 void f2_bar ();
 void f2_cconly (i64 v_a, i64 v_b)
 {
-/* { dg-final { scan-assembler "f2_cconly:\n\trisbg\t%r3,%r2,63,59,0\n\tber\t%r14\n\tjg\tf2_bar\n" { target { lp64 } } } } */
+/* { dg-final { scan-assembler "f2_cconly:\n\trisbg\t%r2,%r3,60,62,0\n\tber\t%r14\n\tjg\tf2_bar\n" { target { lp64 } } } } */
 /* { dg-final { scan-assembler "f2_cconly:\n\trisbgn\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r3,%r5,60,62,0\n\tber\t%r14\n\tjg\tf2_bar\n" { target { ! lp64 } } } } */
   if ((v_a & -15) | (v_b & 14))
     f2_bar();
-- 
2.23.0