* [PATCH 05/21] [arm] Reduce usage of arm_selected_cpu.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
@ 2016-12-15 16:05 ` Richard Earnshaw (lists)
2016-12-15 16:05 ` [PATCH 03/21] [arm] Introduce arm_active_target Richard Earnshaw (lists)
` (19 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:05 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 348 bytes --]
Make more use of the new data structure for initializing existing
variables.
* arm.c (arm_option_override): Use arm_active_target as source of
information for arm_base_arch and arm_arch_name.
* (arm_file_start): Use arm_active_target for core name.
---
gcc/config/arm/arm.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
[-- Attachment #2: 0005-arm-Reduce-usage-of-arm_selected_cpu.patch --]
[-- Type: text/x-patch, Size: 1259 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a4d370c..3806226 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3276,9 +3276,9 @@ arm_option_override (void)
SUBTARGET_OVERRIDE_OPTIONS;
#endif
- sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch);
+ sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name);
insn_flags = arm_selected_cpu->flags;
- arm_base_arch = arm_selected_cpu->base_arch;
+ arm_base_arch = arm_active_target.base_arch;
arm_tune = arm_active_target.tune_core;
tune_flags = arm_active_target.tune_flags;
@@ -26012,12 +26012,13 @@ arm_file_start (void)
arm_active_target.arch_name);
}
}
- else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
- asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_cpu->name + 8);
+ else if (strncmp (arm_active_target.core_name, "generic", 7) == 0)
+ asm_fprintf (asm_out_file, "\t.arch %s\n",
+ arm_active_target.core_name + 8);
else
{
const char* truncated_name
- = arm_rewrite_selected_cpu (arm_selected_cpu->name);
+ = arm_rewrite_selected_cpu (arm_active_target.core_name);
asm_fprintf (asm_out_file, "\t.cpu %s\n", truncated_name);
}
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 03/21] [arm] Introduce arm_active_target.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
2016-12-15 16:05 ` [PATCH 05/21] [arm] Reduce usage of arm_selected_cpu Richard Earnshaw (lists)
@ 2016-12-15 16:05 ` Richard Earnshaw (lists)
2016-12-15 16:05 ` [PATCH 01/21] [arm] Separte tuning flags from architectural flags in CPU tables Richard Earnshaw (lists)
` (18 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:05 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1295 bytes --]
This patch creates a new data structure for carrying around the data
relating to the current compilation target. The idea behind this is
that this data structure can be updated to reflect the overall
compilation target as new information is gathered (from command line
options) or architectural extensions. We will no-longer have to grub
around looking in multiple places for this information.
There are some small behaviour changes around how we handle selecting
a default CPU if thumb or interworking are specified on the command
line and the default CPU does not support thumb, but I believe the
existing code was broken in that respect. This code will go away once
we obsolete pre-armv4t devices.
* arm-protos.h (arm_build_target): New structure.
(arm_active_target): Declare it.
* arm.c (arm_active_target): New variable.
(bitmap_popcount): New function.
(feature_count): Delete.
(arm_initialize_isa): New function.
isa_fpubits): New variable.
(arm_configure_build_target): New function.
(arm_option_override): Initialize isa_fpubits and arm_active_target.isa.
Use arm_configure_build_target.
---
gcc/config/arm/arm-protos.h | 25 ++++++
gcc/config/arm/arm.c | 203
+++++++++++++++++++++++++++++++-------------
2 files changed, 168 insertions(+), 60 deletions(-)
[-- Attachment #2: 0003-arm-Introduce-arm_active_target.patch --]
[-- Type: text/x-patch, Size: 12415 bytes --]
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 58d2ae3..7673e3a 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -449,6 +449,31 @@ extern int arm_arch_no_volatile_ce;
than core registers. */
extern int prefer_neon_for_64bits;
+/* Structure defining the current overall architectural target and tuning. */
+struct arm_build_target
+{
+ /* Name of the target CPU, if known, or NULL if the target CPU was not
+ specified by the user (and inferred from the -march option). */
+ const char *core_name;
+ /* Name of the target ARCH. NULL if there is a selected CPU. */
+ const char *arch_name;
+ /* Preprocessor substring (never NULL). */
+ const char *arch_pp_name;
+ /* CPU identifier for the core we're compiling for (architecturally). */
+ enum processor_type arch_core;
+ /* The base architecture value. */
+ enum base_architecture base_arch;
+ /* Bitmap encapsulating the isa_bits for the target environment. */
+ sbitmap isa;
+ /* Flags used for tuning. Long term, these move into tune_params. */
+ unsigned int tune_flags;
+ /* Tables with more detailed tuning information. */
+ const struct tune_params *tune;
+ /* CPU identifier for the tuning target. */
+ enum processor_type tune_core;
+};
+
+extern struct arm_build_target arm_active_target;
#endif /* ! GCC_ARM_PROTOS_H */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bf04a06..deab528 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -88,7 +88,7 @@ static void arm_add_gc_roots (void);
static int arm_gen_constant (enum rtx_code, machine_mode, rtx,
unsigned HOST_WIDE_INT, rtx, rtx, int, int);
static unsigned bit_count (unsigned long);
-static unsigned feature_count (const arm_feature_set*);
+static unsigned bitmap_popcount (const sbitmap);
static int arm_address_register_rtx_p (rtx, int);
static int arm_legitimate_index_p (machine_mode, rtx, RTX_CODE, int);
static bool is_called_in_ARM_mode (tree);
@@ -791,6 +791,10 @@ unsigned int tune_flags = 0;
target. */
enum base_architecture arm_base_arch = BASE_ARCH_0;
+/* Active target architecture and tuning. */
+
+struct arm_build_target arm_active_target;
+
/* The following are used in the arm.md file as equivalents to bits
in the above two flag variables. */
@@ -2376,12 +2380,17 @@ bit_count (unsigned long value)
return count;
}
-/* Return the number of features in feature-set SET. */
+/* Return the number of bits set in BMAP. */
static unsigned
-feature_count (const arm_feature_set * set)
+bitmap_popcount (const sbitmap bmap)
{
- return (bit_count (ARM_FSET_CPU1 (*set))
- + bit_count (ARM_FSET_CPU2 (*set)));
+ unsigned int count = 0;
+ unsigned int n = 0;
+ sbitmap_iterator sbi;
+
+ EXECUTE_IF_SET_IN_BITMAP (bmap, 0, n, sbi)
+ count++;
+ return count;
}
typedef struct
@@ -3038,100 +3047,149 @@ arm_option_override_internal (struct gcc_options *opts,
#endif
}
-/* Fix up any incompatible options that the user has specified. */
+/* Convert a static initializer array of feature bits to sbitmap
+ representation. */
static void
-arm_option_override (void)
+arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
+{
+ bitmap_clear (isa);
+ while (*isa_bits != isa_nobit)
+ bitmap_set_bit (isa, *(isa_bits++));
+}
+
+static sbitmap isa_fpubits;
+
+/* Configure a build target TARGET from the user-specified options OPTS and
+ OPTS_SET. If WARN_COMPATIBLE, emit a diagnostic if both the CPU and
+ architecture have been specified, but the two are not identical. */
+static void
+arm_configure_build_target (struct arm_build_target *target,
+ struct gcc_options *opts,
+ struct gcc_options *opts_set,
+ bool warn_compatible)
{
arm_selected_arch = NULL;
arm_selected_cpu = NULL;
arm_selected_tune = NULL;
- if (global_options_set.x_arm_arch_option)
- arm_selected_arch = &all_architectures[arm_arch_option];
+ bitmap_clear (target->isa);
+ target->core_name = NULL;
+ target->arch_name = NULL;
+
+ if (opts_set->x_arm_arch_option)
+ arm_selected_arch = &all_architectures[opts->x_arm_arch_option];
- if (global_options_set.x_arm_cpu_option)
+ if (opts_set->x_arm_cpu_option)
{
- arm_selected_cpu = &all_cores[(int) arm_cpu_option];
- arm_selected_tune = &all_cores[(int) arm_cpu_option];
+ arm_selected_cpu = &all_cores[(int) opts->x_arm_cpu_option];
+ arm_selected_tune = &all_cores[(int) opts->x_arm_cpu_option];
}
- if (global_options_set.x_arm_tune_option)
- arm_selected_tune = &all_cores[(int) arm_tune_option];
-
-#ifdef SUBTARGET_OVERRIDE_OPTIONS
- SUBTARGET_OVERRIDE_OPTIONS;
-#endif
+ if (opts_set->x_arm_tune_option)
+ arm_selected_tune = &all_cores[(int) opts->x_arm_tune_option];
if (arm_selected_arch)
{
+ arm_initialize_isa (target->isa, arm_selected_arch->isa_bits);
+
if (arm_selected_cpu)
{
- const arm_feature_set tuning_flags = ARM_FSET_MAKE_CPU1 (FL_TUNE);
- arm_feature_set selected_flags;
- ARM_FSET_XOR (selected_flags, arm_selected_cpu->flags,
- arm_selected_arch->flags);
- ARM_FSET_EXCLUDE (selected_flags, selected_flags, tuning_flags);
- /* Check for conflict between mcpu and march. */
- if (!ARM_FSET_IS_EMPTY (selected_flags))
+ auto_sbitmap cpu_isa (isa_num_bits);
+
+ arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits);
+ bitmap_xor (cpu_isa, cpu_isa, target->isa);
+ /* Ignore (for now) any bits that might be set by -mfpu. */
+ bitmap_and_compl (cpu_isa, cpu_isa, isa_fpubits);
+
+ if (!bitmap_empty_p (cpu_isa))
{
- warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
- arm_selected_cpu->name, arm_selected_arch->name);
+ if (warn_compatible)
+ warning (0, "switch -mcpu=%s conflicts with -march=%s switch",
+ arm_selected_cpu->name, arm_selected_arch->name);
/* -march wins for code generation.
- -mcpu wins for default tuning. */
+ -mcpu wins for default tuning. */
if (!arm_selected_tune)
arm_selected_tune = arm_selected_cpu;
arm_selected_cpu = arm_selected_arch;
}
else
- /* -mcpu wins. */
- arm_selected_arch = NULL;
+ {
+ /* Architecture and CPU are essentially the same.
+ Prefer the CPU setting. */
+ arm_selected_arch = NULL;
+ }
}
else
- /* Pick a CPU based on the architecture. */
- arm_selected_cpu = arm_selected_arch;
+ {
+ /* Pick a CPU based on the architecture. */
+ arm_selected_cpu = arm_selected_arch;
+ target->arch_name = arm_selected_arch->name;
+ }
}
/* If the user did not specify a processor, choose one for them. */
if (!arm_selected_cpu)
{
const struct processors * sel;
- arm_feature_set sought = ARM_FSET_EMPTY;;
+ auto_sbitmap sought_isa (isa_num_bits);
+ bitmap_clear (sought_isa);
+ auto_sbitmap default_isa (isa_num_bits);
arm_selected_cpu = &all_cores[TARGET_CPU_DEFAULT];
gcc_assert (arm_selected_cpu->name);
+ /* RWE: All of the selection logic below (to the end of this
+ 'if' clause) looks somewhat suspect. It appears to be mostly
+ there to support forcing thumb support when the default CPU
+ does not have thumb (somewhat dubious in terms of what the
+ user might be expecting). I think it should be removed once
+ support for the pre-thumb era cores is removed. */
sel = arm_selected_cpu;
- insn_flags = sel->flags;
+ arm_initialize_isa (default_isa, sel->isa_bits);
- /* Now check to see if the user has specified some command line
- switch that require certain abilities from the cpu. */
+ /* Now check to see if the user has specified any command line
+ switches that require certain abilities from the cpu. */
if (TARGET_INTERWORK || TARGET_THUMB)
{
- ARM_FSET_ADD_CPU1 (sought, FL_THUMB);
- ARM_FSET_ADD_CPU1 (sought, FL_MODE32);
+ bitmap_set_bit (sought_isa, isa_bit_thumb);
+ bitmap_set_bit (sought_isa, isa_bit_mode32);
/* There are no ARM processors that support both APCS-26 and
- interworking. Therefore we force FL_MODE26 to be removed
- from insn_flags here (if it was set), so that the search
- below will always be able to find a compatible processor. */
- ARM_FSET_DEL_CPU1 (insn_flags, FL_MODE26);
+ interworking. Therefore we forcibly remove MODE26 from
+ from the isa features here (if it was set), so that the
+ search below will always be able to find a compatible
+ processor. */
+ bitmap_clear_bit (default_isa, isa_bit_mode26);
}
- if (!ARM_FSET_IS_EMPTY (sought)
- && !(ARM_FSET_CPU_SUBSET (sought, insn_flags)))
+ /* If there are such requirements and the default CPU does not
+ satisfy them, we need to run over the complete list of
+ cores looking for one that is satisfactory. */
+ if (!bitmap_empty_p (sought_isa)
+ && !bitmap_subset_p (sought_isa, default_isa))
{
+ auto_sbitmap candidate_isa (isa_num_bits);
+ /* We're only interested in a CPU with at least the
+ capabilities of the default CPU and the required
+ additional features. */
+ bitmap_ior (default_isa, default_isa, sought_isa);
+
/* Try to locate a CPU type that supports all of the abilities
of the default CPU, plus the extra abilities requested by
the user. */
for (sel = all_cores; sel->name != NULL; sel++)
- if (ARM_FSET_CPU_SUBSET (sought, sel->flags))
- break;
+ {
+ arm_initialize_isa (candidate_isa, sel->isa_bits);
+ /* An exact match? */
+ if (bitmap_equal_p (default_isa, candidate_isa))
+ break;
+ }
if (sel->name == NULL)
{
- unsigned current_bit_count = 0;
+ unsigned current_bit_count = isa_num_bits;
const struct processors * best_fit = NULL;
/* Ideally we would like to issue an error message here
@@ -3141,32 +3199,34 @@ arm_option_override (void)
ought to use the -mcpu=<name> command line option to
override the default CPU type.
- If we cannot find a cpu that has both the
- characteristics of the default cpu and the given
+ If we cannot find a CPU that has exactly the
+ characteristics of the default CPU and the given
command line options we scan the array again looking
- for a best match. */
+ for a best match. The best match must have at least
+ the capabilities of the perfect match. */
for (sel = all_cores; sel->name != NULL; sel++)
{
- arm_feature_set required = ARM_FSET_EMPTY;
- ARM_FSET_UNION (required, sought, insn_flags);
- if (ARM_FSET_CPU_SUBSET (required, sel->flags))
+ arm_initialize_isa (candidate_isa, sel->isa_bits);
+
+ if (bitmap_subset_p (default_isa, candidate_isa))
{
unsigned count;
- arm_feature_set flags;
- ARM_FSET_INTER (flags, sel->flags, insn_flags);
- count = feature_count (&flags);
- if (count >= current_bit_count)
+ bitmap_and_compl (candidate_isa, candidate_isa,
+ default_isa);
+ count = bitmap_popcount (candidate_isa);
+
+ if (count < current_bit_count)
{
best_fit = sel;
current_bit_count = count;
}
}
+
+ gcc_assert (best_fit);
+ sel = best_fit;
}
- gcc_assert (best_fit);
- sel = best_fit;
}
-
arm_selected_cpu = sel;
}
}
@@ -3176,6 +3236,29 @@ arm_option_override (void)
if (!arm_selected_tune)
arm_selected_tune = &all_cores[arm_selected_cpu->core];
+ target->arch_pp_name = arm_selected_cpu->arch;
+ target->tune_flags = arm_selected_tune->tune_flags;
+ target->tune = arm_selected_tune->tune;
+}
+
+/* Fix up any incompatible options that the user has specified. */
+static void
+arm_option_override (void)
+{
+ static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit };
+
+ isa_fpubits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_fpubits, fpu_bitlist);
+
+ arm_active_target.isa = sbitmap_alloc (isa_num_bits);
+
+ arm_configure_build_target (&arm_active_target, &global_options,
+ &global_options_set, true);
+
+#ifdef SUBTARGET_OVERRIDE_OPTIONS
+ SUBTARGET_OVERRIDE_OPTIONS;
+#endif
+
sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_selected_cpu->arch);
insn_flags = arm_selected_cpu->flags;
arm_base_arch = arm_selected_cpu->base_arch;
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 01/21] [arm] Separte tuning flags from architectural flags in CPU tables.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
2016-12-15 16:05 ` [PATCH 05/21] [arm] Reduce usage of arm_selected_cpu Richard Earnshaw (lists)
2016-12-15 16:05 ` [PATCH 03/21] [arm] Introduce arm_active_target Richard Earnshaw (lists)
@ 2016-12-15 16:05 ` Richard Earnshaw (lists)
2016-12-15 16:05 ` [PATCH 02/21] [arm] Add new isa bits method Richard Earnshaw (lists)
` (17 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:05 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1863 bytes --]
We start out by separating the 'tuning flags' in a CPU or architecture
specification into a new field in the data structures. Because there
aren't very many of these (and we'd like to get rid of them entirely,
eventually, moving to entries in the tuning tables), we just use a
simple unsigned word. This frees up a number of bits in the main
flags data structure, but we don't consolidate them as we'll be
getting rid of them entirely shortly.
There's one small user-visible change, the slow multiply flag is moved
from being treated as an architectural flag to a tuning flag. This
has two consequences: it's now ignored for architectural matching to a
CPU and specifying a -mtune option will now correctly apply the
multiply performance to the decision as to which sequences to
synthesise.
* arm-arches.def (ARM_ARCH): Add extra field TUNE_FLAGS, move
tuning properties from architectural FLAGS field.
* arm-cores.def (ARM_CORE): Likewise.
* arm-protos.h (TF_LDSCHED, TF_WBUF, TF_CO_PROC): New macros.
(TF_SMALLMUL, TF_STRONG, TF_SCALE, TF_NOMODE32): New macros.
(FL_LDSCHED, FL_STRONG, FL_WBUF, FL_SMALLMUL): Delete.
(FL_TUNE): Remove deleted elements.
(tune_flags): Convert type to unsigned int.
* arm.c (struct processors): Add new field tune_flags.
(all_cores, all_arches): Initialize it.
(arm_option_override): Adapt uses of tune_flags. Use tune_flags
for deciding when we should have slow multiply operations.
---
gcc/common/config/arm/arm-common.c | 4 +-
gcc/config/arm/arm-arches.def | 85 ++++++--------
gcc/config/arm/arm-cores.def | 224
++++++++++++++++++-------------------
gcc/config/arm/arm-flags.h | 24 ++--
gcc/config/arm/arm-opts.h | 2 +-
gcc/config/arm/arm-protos.h | 2 +-
gcc/config/arm/arm.c | 29 ++---
7 files changed, 184 insertions(+), 186 deletions(-)
[-- Attachment #2: 0001-arm-Separte-tuning-flags-from-architectural-flags-in.patch --]
[-- Type: text/x-patch, Size: 43388 bytes --]
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index c0de5d2..93a13c8 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -107,12 +107,12 @@ struct arm_arch_core_flag
static const struct arm_arch_core_flag arm_arch_core_flags[] =
{
#undef ARM_CORE
-#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
{NAME, FLAGS},
#include "config/arm/arm-cores.def"
#undef ARM_CORE
#undef ARM_ARCH
-#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \
{NAME, FLAGS},
#include "config/arm/arm-arches.def"
#undef ARM_ARCH
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 71cabcc..d81a471 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -19,7 +19,7 @@
/* Before using #include to read this file, define a macro:
- ARM_ARCH(NAME, CORE, ARCH, FLAGS)
+ ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS)
The NAME is the name of the architecture, represented as a string
constant. The CORE is the identifier for a core representative of
@@ -28,52 +28,41 @@
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_ARCH("armv2", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv2a", arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv3", arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3))
-ARM_ARCH("armv3m", arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M))
-ARM_ARCH("armv4", arm7tdmi, 4, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4))
+ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
+ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
+ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
-ARM_ARCH("armv4t", arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T))
-ARM_ARCH("armv5", arm10tdmi, 5, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5))
-ARM_ARCH("armv5t", arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5T))
-ARM_ARCH("armv5e", arm1026ejs, 5E, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5E))
-ARM_ARCH("armv5te", arm1026ejs, 5TE, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH5TE))
-ARM_ARCH("armv6", arm1136js, 6, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6))
-ARM_ARCH("armv6j", arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6J))
-ARM_ARCH("armv6k", mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6K))
-ARM_ARCH("armv6z", arm1176jzs, 6Z, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6Z))
-ARM_ARCH("armv6kz", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6zk", arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6t2", arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH6T2))
-ARM_ARCH("armv6-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv6s-m", cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv7", cortexa8, 7, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7))
-ARM_ARCH("armv7-a", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7A))
-ARM_ARCH("armv7ve", cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7VE))
-ARM_ARCH("armv7-r", cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7R))
-ARM_ARCH("armv7-m", cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7M))
-ARM_ARCH("armv7e-m", cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH7EM))
-ARM_ARCH("armv8-a", cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH8A))
-ARM_ARCH("armv8-a+crc",cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A))
-ARM_ARCH("armv8.1-a", cortexa53, 8A,
- ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
- FL2_FOR_ARCH8_1A))
-ARM_ARCH("armv8.1-a+crc",cortexa53, 8A,
- ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
- FL2_FOR_ARCH8_1A))
-ARM_ARCH ("armv8.2-a", cortexa53, 8A,
- ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
- FL2_FOR_ARCH8_2A))
-ARM_ARCH ("armv8.2-a+fp16", cortexa53, 8A,
- ARM_FSET_MAKE (FL_CO_PROC | FL_CRC32 | FL_FOR_ARCH8A,
- FL2_FOR_ARCH8_2A | FL2_FP16INST))
-ARM_ARCH("armv8-m.base", cortexm23, 8M_BASE,
- ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
-ARM_ARCH("armv8-m.main", cortexm7, 8M_MAIN,
- ARM_FSET_MAKE (FL_CO_PROC | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("armv8-m.main+dsp", cortexm33, 8M_MAIN,
- ARM_FSET_MAKE (FL_CO_PROC | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("iwmmxt", iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
-ARM_ARCH("iwmmxt2", iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
+ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
+ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
+ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
+ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
+ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
+ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
+ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
+ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
+ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
+ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
+ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
+ARM_ARCH("armv6-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
+ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
+ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
+ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
+ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
+ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
+ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
+ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A))
+ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
+ARM_ARCH("armv8.1-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
+ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
+ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
+ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
+ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index fd96a41..27b156a 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -25,13 +25,14 @@
/* Before using #include to read this file, define a macro:
- ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, ARCH, FLAGS, COSTS)
+ ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS)
The CORE_NAME is the name of the core, represented as a string constant.
The INTERNAL_IDENT is the name of the core represented as an identifier.
This must be unique for each entry in this table.
The TUNE_IDENT is the name of the core for which scheduling decisions
should be made, represented as an identifier.
+ TUNE_FLAGS is a set of flag bits that are used to affect tuning.
ARCH is the architecture revision implemented by the chip.
FLAGS is the set of feature flags of that core.
This need not include flags implied by the architecture.
@@ -43,145 +44,144 @@
Some tools assume no whitespace up to the first "," in each entry. */
/* V2/V2A Architecture Processors */
-ARM_CORE("arm2", arm2, arm2, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm250", arm250, arm250, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm3", arm3, arm3, 2, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
/* V3 Architecture Processors */
-ARM_CORE("arm6", arm6, arm6, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm60", arm60, arm60, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm600", arm600, arm600, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm610", arm610, arm610, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm620", arm620, arm620, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7", arm7, arm7, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7d", arm7d, arm7d, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7di", arm7di, arm7di, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm70", arm70, arm70, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700", arm700, arm700, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700i", arm700i, arm700i, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710", arm710, arm710, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm720", arm720, arm720, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710c", arm710c, arm710c, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7100", arm7100, arm7100, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7500", arm7500, arm7500, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
/* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe, 3, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_WBUF | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
/* V3M Architecture Processors */
/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
those don't alter the code, so arm7m is sometimes used. */
-ARM_CORE("arm7m", arm7m, arm7m, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dm", arm7dm, arm7dm, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi, 3M, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
/* V4 Architecture Processors */
-ARM_CORE("arm8", arm8, arm8, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul)
-ARM_CORE("arm810", arm810, arm810, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_FOR_ARCH4), fastmul)
-ARM_CORE("strongarm", strongarm, strongarm, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm110", strongarm110, strongarm110, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_LDSCHED | FL_STRONG | FL_FOR_ARCH4), strongarm)
-ARM_CORE("fa526", fa526, fa526, 4, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul)
-ARM_CORE("fa626", fa626, fa626, 4, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
+ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
/* V4T Architecture Processors */
-ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, 4T, ARM_FSET_MAKE_CPU1 (FL_CO_PROC | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm710t", arm710t, arm710t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm720t", arm720t, arm720t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm740t", arm740t, arm740t, 4T, ARM_FSET_MAKE_CPU1 (FL_WBUF | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9", arm9, arm9, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920", arm920, arm920, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920t", arm920t, arm920t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm922t", arm922t, arm922t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm940t", arm940t, arm940t, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
-ARM_CORE("ep9312", ep9312, ep9312, 4T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
/* V5T Architecture Processors */
-ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, 5T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul)
-ARM_CORE("arm1020t", arm1020t, arm1020t, 5T, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
/* V5TE Architecture Processors */
-ARM_CORE("arm9e", arm9e, arm9e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm946e-s", arm946es, arm946es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm966e-s", arm966es, arm966es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm968e-s", arm968es, arm968es, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm10e", arm10e, arm10e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1020e", arm1020e, arm1020e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1022e", arm1022e, arm1022e, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("xscale", xscale, xscale, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt", iwmmxt, iwmmxt, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_STRONG | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("fa606te", fa606te, fa606te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa626te", fa626te, fa626te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fmp626", fmp626, fmp626, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa726te", fa726te, fa726te, 5TE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TE), fa726te)
+ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
/* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e)
-ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
/* V6 Architecture Processors */
-ARM_CORE("arm1136j-s", arm1136js, arm1136js, 6J, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, 6J, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, 6KZ, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, 6K, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6K), 9e)
-ARM_CORE("mpcore", mpcore, mpcore, 6K, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6K), 9e)
-ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, 6T2, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6T2), v6t2)
-ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, 6T2, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
+ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
+ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
+ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
+ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
/* V6M Architecture Processors */
-ARM_CORE("cortex-m1", cortexm1, cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0", cortexm0, cortexm0, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
/* V6M Architecture Processors for small-multiply implementations. */
-ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, 6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus,6M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_SMALLMUL | FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
/* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a", genericv7a, genericv7a, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex)
-ARM_CORE("cortex-a5", cortexa5, cortexa5, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a5)
-ARM_CORE("cortex-a7", cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
-ARM_CORE("cortex-a8", cortexa8, cortexa8, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a8)
-ARM_CORE("cortex-a9", cortexa9, cortexa9, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), cortex_a9)
-ARM_CORE("cortex-a12", cortexa12, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-a15", cortexa15, cortexa15, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17", cortexa17, cortexa17, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-r4", cortexr4, cortexr4, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r5", cortexr5, cortexr5, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r7", cortexr7, cortexr7, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r8", cortexr8, cortexr7, 7R, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-m7", cortexm7, cortexm7, 7EM, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
-ARM_CORE("cortex-m4", cortexm4, cortexm4, 7EM, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3", cortexm3, cortexm3, 7M, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7M), v7m)
-ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH7A), marvell_pj4)
+ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
+ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
+ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
+ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
+ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
+ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
+ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
+ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
+ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
/* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
/* V8 Architecture Processors */
-ARM_CORE("cortex-a32", cortexa32, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
-ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-m23", cortexm23, cortexm23, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m)
-ARM_CORE("cortex-m33", cortexm33, cortexm33, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
-ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
-ARM_CORE("falkor", falkor, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("xgene1", xgene1, xgene1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8A), xgene1)
+ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
+ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
+ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
+ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A), xgene1)
/* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h
index fb49838..6482c64 100644
--- a/gcc/config/arm/arm-flags.h
+++ b/gcc/config/arm/arm-flags.h
@@ -22,6 +22,16 @@
#ifndef GCC_ARM_FLAGS_H
#define GCC_ARM_FLAGS_H
+/* Flags used to identify a few tuning properties. These are for legacy
+ purposes only. Do not add any more of these: use the main tuning tables. */
+#define TF_LDSCHED (1U << 0)
+#define TF_WBUF (1U << 1)
+#define TF_CO_PROC (1U << 2)
+#define TF_SMALLMUL (1U << 3)
+#define TF_STRONG (1U << 4)
+#define TF_XSCALE (1U << 5)
+#define TF_NO_MODE32 (1U << 6)
+
/* Flags used to identify the presence of processor capabilities. */
/* Bit values used to identify processor capabilities. */
@@ -34,16 +44,15 @@
#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
#define FL_THUMB (1U << 6) /* Thumb aware. */
-#define FL_LDSCHED (1U << 7) /* Load scheduling necessary. */
-#define FL_STRONG (1U << 8) /* StrongARM. */
+/* Spare (1U << 7) */
+/* Spare (1U << 8) */
#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
#define FL_XSCALE (1U << 10) /* XScale. */
-/* spare (1U << 11) */
+/* Spare (1U << 11) */
#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
media instructions. */
#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
-#define FL_WBUF (1U << 14) /* Schedule for write buffer ops.
- Note: ARM6 & 7 derivatives only. */
+/* Spare (1U << 14) */
#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
#define FL_THUMB2 (1U << 16) /* Thumb-2. */
#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
@@ -57,7 +66,7 @@
#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
#define FL_ARCH8 (1U << 24) /* Architecture 8. */
#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
-#define FL_SMALLMUL (1U << 26) /* Small multiply supported. */
+/* Spare (1U << 26) */
#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
@@ -73,8 +82,7 @@
#define FL2_CMSE (1U << 3) /* ARMv8-M Security Extensions. */
/* Flags that only effect tuning, not available instructions. */
-#define FL_TUNE (FL_WBUF | FL_VFPV2 | FL_STRONG | FL_LDSCHED \
- | FL_CO_PROC)
+#define FL_TUNE (FL_VFPV2)
#define FL_FOR_ARCH2 FL_NOTM
#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index e06fedb..6f15065 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -31,7 +31,7 @@
enum processor_type
{
#undef ARM_CORE
-#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
TARGET_CPU_##INTERNAL_IDENT,
#include "arm-cores.def"
#undef ARM_CORE
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 05d73ab..2ec9a4e3 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -358,7 +358,7 @@ extern arm_feature_set insn_flags;
/* The bits in this mask specify which instruction scheduling options should
be used. */
-extern arm_feature_set tune_flags;
+extern unsigned int tune_flags;
/* Nonzero if this chip supports the ARM Architecture 3M extensions. */
extern int arm_arch3m;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 437da6f..2caaba4 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -785,7 +785,7 @@ arm_feature_set insn_flags = ARM_FSET_EMPTY;
/* The bits in this mask specify which instruction scheduling options should
be used. */
-arm_feature_set tune_flags = ARM_FSET_EMPTY;
+unsigned int tune_flags = 0;
/* The highest ARM architecture version supported by the
target. */
@@ -950,6 +950,7 @@ struct processors
{
const char *const name;
enum processor_type core;
+ unsigned int tune_flags;
const char *arch;
enum base_architecture base_arch;
const arm_feature_set flags;
@@ -2287,12 +2288,12 @@ const struct tune_params arm_fa726te_tune =
static const struct processors all_cores[] =
{
/* ARM Cores */
-#define ARM_CORE(NAME, X, IDENT, ARCH, FLAGS, COSTS) \
- {NAME, TARGET_CPU_##IDENT, #ARCH, BASE_ARCH_##ARCH, \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+ {NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
FLAGS, &arm_##COSTS##_tune},
#include "arm-cores.def"
#undef ARM_CORE
- {NULL, TARGET_CPU_arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
+ {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
};
static const struct processors all_architectures[] =
@@ -2301,11 +2302,11 @@ static const struct processors all_architectures[] =
/* We don't specify tuning costs here as it will be figured out
from the core. */
-#define ARM_ARCH(NAME, CORE, ARCH, FLAGS) \
- {NAME, TARGET_CPU_##CORE, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \
+ {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
#include "arm-arches.def"
#undef ARM_ARCH
- {NULL, TARGET_CPU_arm_none, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
+ {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
};
@@ -3177,7 +3178,7 @@ arm_option_override (void)
arm_base_arch = arm_selected_cpu->base_arch;
arm_tune = arm_selected_tune->core;
- tune_flags = arm_selected_tune->flags;
+ tune_flags = arm_selected_tune->tune_flags;
current_tune = arm_selected_tune->tune;
/* TBD: Dwarf info for apcs frame is not handled yet. */
@@ -3228,10 +3229,10 @@ arm_option_override (void)
arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
- arm_ld_sched = ARM_FSET_HAS_CPU1 (tune_flags, FL_LDSCHED);
- arm_tune_strongarm = ARM_FSET_HAS_CPU1 (tune_flags, FL_STRONG);
- arm_tune_wbuf = ARM_FSET_HAS_CPU1 (tune_flags, FL_WBUF);
- arm_tune_xscale = ARM_FSET_HAS_CPU1 (tune_flags, FL_XSCALE);
+ arm_ld_sched = (tune_flags & TF_LDSCHED) != 0;
+ arm_tune_strongarm = (tune_flags & TF_STRONG) != 0;
+ arm_tune_wbuf = (tune_flags & TF_WBUF) != 0;
+ arm_tune_xscale = (tune_flags & TF_XSCALE) != 0;
arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT);
arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2);
arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV);
@@ -3240,7 +3241,7 @@ arm_option_override (void)
arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0;
arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE);
- arm_m_profile_small_mul = ARM_FSET_HAS_CPU1 (insn_flags, FL_SMALLMUL);
+ arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0;
arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST);
if (arm_fp16_inst)
{
@@ -3324,7 +3325,7 @@ arm_option_override (void)
/* For arm2/3 there is no need to do any scheduling if we are doing
software floating-point. */
- if (TARGET_SOFT_FLOAT && !ARM_FSET_HAS_CPU1 (tune_flags, FL_MODE32))
+ if (TARGET_SOFT_FLOAT && (tune_flags & TF_NO_MODE32))
flag_schedule_insns = flag_schedule_insns_after_reload = 0;
/* Use the cp15 method if it is available. */
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 02/21] [arm] Add new isa bits method
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (2 preceding siblings ...)
2016-12-15 16:05 ` [PATCH 01/21] [arm] Separte tuning flags from architectural flags in CPU tables Richard Earnshaw (lists)
@ 2016-12-15 16:05 ` Richard Earnshaw (lists)
2016-12-15 16:06 ` [PATCH 08/21] [arm] Remove insn_flags Richard Earnshaw (lists)
` (16 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:05 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1521 bytes --]
This patch adds the new ISA data structures. The idea is to use an
sbitmap for carrying these around internally. We don't make much use
of this yet, but will increasingly migrate over to this in the
following patches. All cores and architectures currently have both
old and new encodings for now.
For simplicity and clarity we introduce internally the concept of
ARMv7ve. It doesn't change any visible behaviour.
There's also a bit of tidying up of the various supported cores,
sorting them by profile.
* arm-isa.h: New file.
* arm-protos.h: Include it.
* arm-arches.def: Add new ISA field to all entries. Drop bogus
armv8.1-a+crc architecture.
* arm-cores.def: Similarly. Group ARMv8 cores by profile.
* arm-opts.h (enum processor_type): Adjust for new field.
* arm.c (struct processors): New field 'isa_bits'.
(all_cores, all_architectures): Initialize new field.
* arm-tables.opt: Regenerated.
* arm-tune.md: Regenerated.
---
gcc/common/config/arm/arm-common.c | 4 +-
gcc/config/arm/arm-arches.def | 78 ++++++------
gcc/config/arm/arm-cores.def | 235
+++++++++++++++++++------------------
gcc/config/arm/arm-isa.h | 127 ++++++++++++++++++++
gcc/config/arm/arm-opts.h | 2 +-
gcc/config/arm/arm-protos.h | 1 +
gcc/config/arm/arm-tables.opt | 29 ++---
gcc/config/arm/arm-tune.md | 8 +-
gcc/config/arm/arm.c | 15 ++-
9 files changed, 315 insertions(+), 184 deletions(-)
create mode 100644 gcc/config/arm/arm-isa.h
[-- Attachment #2: 0002-arm-Add-new-isa-bits-method.patch --]
[-- Type: text/x-patch, Size: 52784 bytes --]
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index 93a13c8..79e3f1f 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -107,12 +107,12 @@ struct arm_arch_core_flag
static const struct arm_arch_core_flag arm_arch_core_flags[] =
{
#undef ARM_CORE
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
{NAME, FLAGS},
#include "config/arm/arm-cores.def"
#undef ARM_CORE
#undef ARM_ARCH
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS) \
{NAME, FLAGS},
#include "config/arm/arm-arches.def"
#undef ARM_ARCH
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index d81a471..02ece42 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -19,50 +19,50 @@
/* Before using #include to read this file, define a macro:
- ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS)
+ ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)
The NAME is the name of the architecture, represented as a string
constant. The CORE is the identifier for a core representative of
- this architecture. ARCH is the architecture revision. FLAGS is
- the set of feature flags implied by the architecture.
+ this architecture. ARCH is the architecture revision. ISA is the
+ detailed architectural capabilities of the core (see arm-isa.h).
+ FLAGS is the set of feature flags implied by the architecture.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
-ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
-ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
+ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
+ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
+ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
+ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
-ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
-ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
-ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
-ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
-ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
-ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
-ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
-ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
-ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
-ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
-ARM_ARCH("armv6-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
-ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
-ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
-ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
-ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
-ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
-ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
-ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A))
-ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
-ARM_ARCH("armv8.1-a+crc",cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
-ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
-ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
-ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
-ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
-ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
+ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ISA_FEAT(ISA_ARMv5), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
+ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
+ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ISA_FEAT(ISA_ARMv5e), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
+ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
+ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ISA_FEAT(ISA_ARMv6), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
+ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
+ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
+ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ISA_FEAT(ISA_ARMv6z), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
+ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
+ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
+ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
+ARM_ARCH("armv6-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
+ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ISA_FEAT(ISA_ARMv7), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
+ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
+ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
+ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
+ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
+ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
+ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
+ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A))
+ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_1a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
+ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
+ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
+ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
+ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main), ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
+ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
+ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 27b156a..7c951f3 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -25,7 +25,7 @@
/* Before using #include to read this file, define a macro:
- ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS)
+ ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)
The CORE_NAME is the name of the core, represented as a string constant.
The INTERNAL_IDENT is the name of the core represented as an identifier.
@@ -34,6 +34,7 @@
should be made, represented as an identifier.
TUNE_FLAGS is a set of flag bits that are used to affect tuning.
ARCH is the architecture revision implemented by the chip.
+ ISA is the detailed architectural capabilities of the core (see arm-isa.h).
FLAGS is the set of feature flags of that core.
This need not include flags implied by the architecture.
COSTS is the name of the rtx_costs routine to use.
@@ -44,144 +45,146 @@
Some tools assume no whitespace up to the first "," in each entry. */
/* V2/V2A Architecture Processors */
-ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
/* V3 Architecture Processors */
-ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-/* Doesn't have an external co-proc, but does have embedded fpa. */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+/* Doesn't have an external co-proc, but does have embedded fpa (fpa no-longer supported). */
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
/* V3M Architecture Processors */
/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
those don't alter the code, so arm7m is sometimes used. */
-ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
/* V4 Architecture Processors */
-ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
-ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
+ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
+ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
/* V4T Architecture Processors */
-ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
/* V5T Architecture Processors */
-ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
-ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
/* V5TE Architecture Processors */
-ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
+ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
+ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
+ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
+ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
/* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
-ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
/* V6 Architecture Processors */
-ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
-ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
-ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
-ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
+ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
+ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
+ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
+ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
+ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
/* V6M Architecture Processors */
-ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
/* V6M Architecture Processors for small-multiply implementations. */
-ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
/* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
-ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
-ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
-ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
-ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
-ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
-ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
-ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
+ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
+ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
+ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
+ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
+ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
+ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
+ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
+ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
+ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
+ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
/* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-
-/* V8 Architecture Processors */
-ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
-ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
-ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
-ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
-ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A), xgene1)
-
-/* V8 big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+
+/* V8 A-profile Architecture Processors */
+ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
+ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
+ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
+ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
+ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A), xgene1)
+
+/* V8 A-profile big.LITTLE implementations */
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
+ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+
+/* V8 M-profile implementations. */
+ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
+ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
new file mode 100644
index 0000000..15eb6e1
--- /dev/null
+++ b/gcc/config/arm/arm-isa.h
@@ -0,0 +1,127 @@
+/* ISA feature bits for ARM.
+ Copyright (C) 2016 Free Software Foundation, Inc.
+ Contributed by ARM Ltd.
+
+ This file is part of GCC.
+
+ GCC is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published
+ by the Free Software Foundation; either version 3, or (at your
+ option) any later version.
+
+ GCC is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
+
+ Under Section 7 of GPL version 3, you are granted additional
+ permissions described in the GCC Runtime Library Exception, version
+ 3.1, as published by the Free Software Foundation.
+
+ You should have received a copy of the GNU General Public License and
+ a copy of the GCC Runtime Library Exception along with this program;
+ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
+ <http://www.gnu.org/licenses/>. */
+
+#ifndef ARM_ISA_FEATURE_H
+#define ARM_ISA_FEATURE_H
+
+enum isa_feature
+ {
+ isa_nobit, /* Must be first. */
+ isa_bit_ARMv3m, /* Extended multiply. */
+ isa_bit_mode26, /* 26-bit mode support. */
+ isa_bit_mode32, /* 32-bit mode support. */
+ isa_bit_ARMv4, /* Architecture rel 4. */
+ isa_bit_ARMv5, /* Architecture rel 5. */
+ isa_bit_thumb, /* Thumb aware. */
+ isa_bit_ARMv5e, /* Architecture rel 5e. */
+ isa_bit_xscale, /* XScale. */
+ isa_bit_ARMv6, /* Architecture rel 6. */
+ isa_bit_ARMv6k, /* Architecture rel 6k. */
+ isa_bit_thumb2, /* Thumb-2. */
+ isa_bit_notm, /* Instructions that are not present in 'M' profile. */
+ isa_bit_tdiv, /* Thumb division instructions. */
+ isa_bit_ARMv7em, /* Architecture rel 7e-m. */
+ isa_bit_ARMv7, /* Architecture rel 7. */
+ isa_bit_adiv, /* ARM division instructions. */
+ isa_bit_ARMv8, /* Architecture rel 8. */
+ isa_bit_crc32, /* ARMv8 CRC32 instructions. */
+ isa_bit_iwmmxt, /* XScale v2 (Wireless MMX). */
+ isa_bit_iwmmxt2, /* XScale Wireless MMX2. */
+ isa_bit_ARMv8_1, /* Architecture rel 8.1. */
+ isa_bit_ARMv8_2, /* Architecutre rel 8.2. */
+ isa_bit_cmse, /* M-Profile security extensions. */
+ /* Floating point and Neon extensions. */
+ isa_bit_VFPv2, /* Vector floating point v2 (our base level). */
+ isa_bit_VFPv3, /* Vector floating point v3. */
+ isa_bit_neon, /* Advanced SIMD instructions. */
+ isa_bit_fp16, /* FP16 extension (half-precision float). */
+
+ /* ISA Quirks (errata?). */
+ isa_quirk_no_volatile_ce, /* No volatile memory in IT blocks. */
+ isa_quirk_ARMv6kz, /* Previously mis-identified by GCC. */
+
+ /* Aren't currently, but probably should be tuning bits. */
+ isa_bit_smallmul, /* Slow multiply operations. */
+
+ /* Tuning bits. Should be elsewhere. */
+ isa_tune_co_proc, /* Has co-processor bus. */
+ isa_tune_ldsched, /* Load scheduling necessary. */
+ isa_tune_strong, /* StrongARM. */
+ isa_tune_wbuf, /* Schedule for write buffer ops (ARM6 & 7 only). */
+
+ /* Must be last, used to dimension arrays. */
+ isa_num_bits
+ };
+
+/* Helper macros for use when defining CPUs and architectures.
+
+ There must be no parenthesees in these lists, since they are used
+ to initialize arrays. */
+
+#define ISA_ARMv2 isa_bit_notm
+#define ISA_ARMv3 ISA_ARMv2, isa_bit_mode32
+#define ISA_ARMv3m ISA_ARMv3, isa_bit_ARMv3m
+#define ISA_ARMv4 ISA_ARMv3m, isa_bit_ARMv4
+#define ISA_ARMv4t ISA_ARMv4, isa_bit_thumb
+#define ISA_ARMv5 ISA_ARMv4, isa_bit_ARMv5
+#define ISA_ARMv5t ISA_ARMv5, isa_bit_thumb
+#define ISA_ARMv5e ISA_ARMv5, isa_bit_ARMv5e
+#define ISA_ARMv5te ISA_ARMv5e, isa_bit_thumb
+#define ISA_ARMv5tej ISA_ARMv5te
+#define ISA_ARMv6 ISA_ARMv5te, isa_bit_ARMv6
+#define ISA_ARMv6j ISA_ARMv6
+#define ISA_ARMv6k ISA_ARMv6, isa_bit_ARMv6k
+#define ISA_ARMv6z ISA_ARMv6
+#define ISA_ARMv6kz ISA_ARMv6k, isa_quirk_ARMv6kz
+#define ISA_ARMv6zk ISA_ARMv6k
+#define ISA_ARMv6t2 ISA_ARMv6, isa_bit_thumb2
+
+/* This is suspect. ARMv6-m doesn't really pull in any useful features
+ from ARMv5* or ARMv6. */
+#define ISA_ARMv6m isa_bit_mode32, isa_bit_ARMv3m, isa_bit_ARMv4, \
+ isa_bit_thumb, isa_bit_ARMv5, isa_bit_ARMv5e, isa_bit_ARMv6
+/* This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
+ integer SIMD instructions that are in ARMv6T2. */
+#define ISA_ARMv7 ISA_ARMv6m, isa_bit_thumb2, isa_bit_ARMv7
+#define ISA_ARMv7a ISA_ARMv7, isa_bit_notm, isa_bit_ARMv6k
+#define ISA_ARMv7ve ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv
+#define ISA_ARMv7r ISA_ARMv7a, isa_bit_tdiv
+#define ISA_ARMv7m ISA_ARMv7, isa_bit_tdiv
+#define ISA_ARMv7em ISA_ARMv7m, isa_bit_ARMv7em
+#define ISA_ARMv8a ISA_ARMv7ve, isa_bit_ARMv8
+#define ISA_ARMv8_1a ISA_ARMv8a, isa_bit_crc32, isa_bit_ARMv8_1
+#define ISA_ARMv8_2a ISA_ARMv8_1a, isa_bit_ARMv8_2
+#define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
+#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
+
+/* List of all FPU bits to strip out if -mfpu is used to override the
+ default. */
+#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_neon
+
+/* Helper macro so that we can concatenate multiple features together
+ with arm-*.def files, since macro substitution can't have commas within an
+ argument that lacks parenthesis. */
+#define ISA_FEAT(X) X,
+#endif
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index 6f15065..a62ac46 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -31,7 +31,7 @@
enum processor_type
{
#undef ARM_CORE
-#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
TARGET_CPU_##INTERNAL_IDENT,
#include "arm-cores.def"
#undef ARM_CORE
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 2ec9a4e3..58d2ae3 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -23,6 +23,7 @@
#define GCC_ARM_PROTOS_H
#include "arm-flags.h"
+#include "arm-isa.h"
extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
extern int use_return_insn (int, rtx);
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index b5e12dc..9d83379 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -325,12 +325,6 @@ EnumValue
Enum(processor_type) String(cortex-a73) Value( TARGET_CPU_cortexa73)
EnumValue
-Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
-
-EnumValue
-Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
-
-EnumValue
Enum(processor_type) String(exynos-m1) Value( TARGET_CPU_exynosm1)
EnumValue
@@ -354,6 +348,12 @@ Enum(processor_type) String(cortex-a73.cortex-a35) Value( TARGET_CPU_cortexa73co
EnumValue
Enum(processor_type) String(cortex-a73.cortex-a53) Value( TARGET_CPU_cortexa73cortexa53)
+EnumValue
+Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23)
+
+EnumValue
+Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33)
+
Enum
Name(arm_arch) Type(int)
Known ARM architectures (for use with the -march= option):
@@ -443,28 +443,25 @@ EnumValue
Enum(arm_arch) String(armv8.1-a) Value(27)
EnumValue
-Enum(arm_arch) String(armv8.1-a+crc) Value(28)
-
-EnumValue
-Enum(arm_arch) String(armv8.2-a) Value(29)
+Enum(arm_arch) String(armv8.2-a) Value(28)
EnumValue
-Enum(arm_arch) String(armv8.2-a+fp16) Value(30)
+Enum(arm_arch) String(armv8.2-a+fp16) Value(29)
EnumValue
-Enum(arm_arch) String(armv8-m.base) Value(31)
+Enum(arm_arch) String(armv8-m.base) Value(30)
EnumValue
-Enum(arm_arch) String(armv8-m.main) Value(32)
+Enum(arm_arch) String(armv8-m.main) Value(31)
EnumValue
-Enum(arm_arch) String(armv8-m.main+dsp) Value(33)
+Enum(arm_arch) String(armv8-m.main+dsp) Value(32)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(34)
+Enum(arm_arch) String(iwmmxt) Value(33)
EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(35)
+Enum(arm_arch) String(iwmmxt2) Value(34)
Enum
Name(arm_fpu) Type(int)
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index 4c92927..22e4a53 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -34,8 +34,8 @@
cortexm3,marvell_pj4,cortexa15cortexa7,
cortexa17cortexa7,cortexa32,cortexa35,
cortexa53,cortexa57,cortexa72,
- cortexa73,cortexm23,cortexm33,
- exynosm1,falkor,qdf24xx,
- xgene1,cortexa57cortexa53,cortexa72cortexa53,
- cortexa73cortexa35,cortexa73cortexa53"
+ cortexa73,exynosm1,falkor,
+ qdf24xx,xgene1,cortexa57cortexa53,
+ cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,
+ cortexm23,cortexm33"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 2caaba4..bf04a06 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -953,6 +953,7 @@ struct processors
unsigned int tune_flags;
const char *arch;
enum base_architecture base_arch;
+ enum isa_feature isa_bits[isa_num_bits];
const arm_feature_set flags;
const struct tune_params *const tune;
};
@@ -2288,12 +2289,13 @@ const struct tune_params arm_fa726te_tune =
static const struct processors all_cores[] =
{
/* ARM Cores */
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
{NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
- FLAGS, &arm_##COSTS##_tune},
+ {ISA isa_nobit}, FLAGS, &arm_##COSTS##_tune},
#include "arm-cores.def"
#undef ARM_CORE
- {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
+ {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit},
+ ARM_FSET_EMPTY, NULL}
};
static const struct processors all_architectures[] =
@@ -2302,11 +2304,12 @@ static const struct processors all_architectures[] =
/* We don't specify tuning costs here as it will be figured out
from the core. */
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, FLAGS) \
- {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, FLAGS, NULL},
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS) \
+ {NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
+ {ISA isa_nobit}, FLAGS, NULL},
#include "arm-arches.def"
#undef ARM_ARCH
- {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, ARM_FSET_EMPTY, NULL}
+ {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, ARM_FSET_EMPTY, NULL}
};
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 08/21] [arm] Remove insn_flags.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (3 preceding siblings ...)
2016-12-15 16:05 ` [PATCH 02/21] [arm] Add new isa bits method Richard Earnshaw (lists)
@ 2016-12-15 16:06 ` Richard Earnshaw (lists)
2016-12-15 16:06 ` [PATCH 11/21] [arm] Delete unused arm_fp_model Richard Earnshaw (lists)
` (15 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:06 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1115 bytes --]
This patch finishes the job of removing insn_flags and moves the logic
over to using the new data structures. I've added a new boolean
variable to detect when we have ARMv7ve-like capabilities and thus
have 64-bit atomic operations since that would be a complex query and
expensive to do in full. It might be better to add a specific bit to
the ISA data structures to indicate this capability directly.
* arm-protos.h (insn_flags): Delete declaration.
(arm_arch7ve): Declare.
* arm.c (insn_flags): Delete.
(arm_arch7ve): New variable.
(arm_selected_cpu): Delete.
(arm_option_check_internal): Use new ISA bitmap.
(arm_option_override_internal): Likewise.
(arm_configure_build_target): Declare arm_selected_cpu locally.
(arm_option_override): Use new ISA bitmap. Initialize arm_arch7ve.
Rearrange variable intialization by general function.
* arm.h (TARGET_HAVE_LPAE): Use arm_arch7ve.
---
gcc/config/arm/arm-protos.h | 7 ++-
gcc/config/arm/arm.c | 103
+++++++++++++++++++++++---------------------
gcc/config/arm/arm.h | 3 +-
3 files changed, 57 insertions(+), 56 deletions(-)
[-- Attachment #2: 0008-arm-Remove-insn_flags.patch --]
[-- Type: text/x-patch, Size: 10342 bytes --]
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 7673e3a..659959b 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -353,10 +353,6 @@ extern void arm_cpu_cpp_builtins (struct cpp_reader *);
extern bool arm_is_constant_pool_ref (rtx);
-/* The bits in this mask specify which
- instructions we are allowed to generate. */
-extern arm_feature_set insn_flags;
-
/* The bits in this mask specify which instruction scheduling options should
be used. */
extern unsigned int tune_flags;
@@ -391,6 +387,9 @@ extern int arm_arch6m;
/* Nonzero if this chip supports the ARM 7 extensions. */
extern int arm_arch7;
+/* Nonzero if this chip supports the ARM 7ve extensions. */
+extern int arm_arch7ve;
+
/* Nonzero if instructions not present in the 'M' profile can be used. */
extern int arm_arch_notm;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c6be4d8..0b82714 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -779,10 +779,6 @@ int arm_fpu_attr;
rtx thumb_call_via_label[14];
static int thumb_call_reg_needed;
-/* The bits in this mask specify which
- instructions we are allowed to generate. */
-arm_feature_set insn_flags = ARM_FSET_EMPTY;
-
/* The bits in this mask specify which instruction scheduling options should
be used. */
unsigned int tune_flags = 0;
@@ -828,6 +824,9 @@ int arm_arch6m = 0;
/* Nonzero if this chip supports the ARM 7 extensions. */
int arm_arch7 = 0;
+/* Nonzero if this chip supports the ARM 7ve extensions. */
+int arm_arch7ve = 0;
+
/* Nonzero if instructions not present in the 'M' profile can be used. */
int arm_arch_notm = 0;
@@ -2316,11 +2315,6 @@ static const struct processors all_architectures[] =
{NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, ARM_FSET_EMPTY, NULL}
};
-
-/* These are populated as commandline arguments are processed, or NULL
- if not specified. */
-static const struct processors *arm_selected_cpu;
-
/* The name of the preprocessor macro to define for this architecture. PROFILE
is replaced by the architecture name (eg. 8A) in arm_option_override () and
is thus chosen to be big enough to hold the longest architecture name. */
@@ -2821,13 +2815,14 @@ arm_option_check_internal (struct gcc_options *opts)
const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index];
/* iWMMXt and NEON are incompatible. */
- if (TARGET_IWMMXT
- && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
+ if (TARGET_IWMMXT
+ && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
error ("iWMMXt and NEON are incompatible");
/* Make sure that the processor choice does not conflict with any of the
other command line choices. */
- if (TARGET_ARM_P (flags) && !ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM))
+ if (TARGET_ARM_P (flags)
+ && !bitmap_bit_p (arm_active_target.isa, isa_bit_notm))
error ("target CPU does not support ARM mode");
/* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
@@ -2949,7 +2944,7 @@ arm_option_override_internal (struct gcc_options *opts,
{
arm_override_options_after_change_1 (opts);
- if (TARGET_INTERWORK && !ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB))
+ if (TARGET_INTERWORK && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb))
{
/* The default is to enable interworking, so this warning message would
be confusing to users who have just compiled with, eg, -march=armv3. */
@@ -2958,7 +2953,7 @@ arm_option_override_internal (struct gcc_options *opts,
}
if (TARGET_THUMB_P (opts->x_target_flags)
- && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB)))
+ && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb))
{
warning (0, "target CPU does not support THUMB instructions");
opts->x_target_flags &= ~MASK_THUMB;
@@ -3069,8 +3064,7 @@ arm_configure_build_target (struct arm_build_target *target,
{
const struct processors *arm_selected_tune = NULL;
const struct processors *arm_selected_arch = NULL;
-
- arm_selected_cpu = NULL;
+ const struct processors *arm_selected_cpu = NULL;
bitmap_clear (target->isa);
target->core_name = NULL;
@@ -3284,7 +3278,6 @@ arm_option_override (void)
#endif
sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name);
- insn_flags = arm_selected_cpu->flags;
arm_base_arch = arm_active_target.base_arch;
arm_tune = arm_active_target.tune_core;
@@ -3298,7 +3291,8 @@ arm_option_override (void)
/* BPABI targets use linker tricks to allow interworking on cores
without thumb support. */
if (TARGET_INTERWORK
- && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB) || TARGET_BPABI))
+ && !TARGET_BPABI
+ && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb))
{
warning (0, "target CPU does not support interworking" );
target_flags &= ~MASK_INTERWORK;
@@ -3319,46 +3313,55 @@ arm_option_override (void)
if (TARGET_APCS_REENT)
warning (0, "APCS reentrant code not supported. Ignored");
- /* Initialize boolean versions of the flags, for use in the arm.md file. */
- arm_arch3m = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH3M);
- arm_arch4 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH4);
- arm_arch4t = arm_arch4 && (ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB));
- arm_arch5 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5);
- arm_arch5e = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5E);
- arm_arch6 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6);
- arm_arch6k = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6K);
- arm_arch6kz = arm_arch6k && ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6KZ);
- arm_arch_notm = ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM);
+ /* Initialize boolean versions of the architectural flags, for use
+ in the arm.md file. */
+ arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv3m);
+ arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv4);
+ arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
+ arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5);
+ arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5e);
+ arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6);
+ arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6k);
+ arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm);
arm_arch6m = arm_arch6 && !arm_arch_notm;
- arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7);
- arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM);
- arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8);
- arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1);
- arm_arch8_2 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_2);
- arm_arch_thumb1 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB);
- arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2);
- arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE);
+ arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7);
+ arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7em);
+ arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8);
+ arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_1);
+ arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_2);
+ arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
+ arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
+ arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
+ arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt);
+ arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2);
+ arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv);
+ arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv);
+ arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32);
+ arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse);
+ arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16);
+ arm_arch7ve
+ = (arm_arch6k && arm_arch7 && arm_arch_thumb_hwdiv && arm_arch_arm_hwdiv);
+ if (arm_fp16_inst)
+ {
+ if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
+ error ("selected fp16 options are incompatible.");
+ arm_fp16_format = ARM_FP16_FORMAT_IEEE;
+ }
+
+ /* Set up some tuning parameters. */
arm_ld_sched = (tune_flags & TF_LDSCHED) != 0;
arm_tune_strongarm = (tune_flags & TF_STRONG) != 0;
arm_tune_wbuf = (tune_flags & TF_WBUF) != 0;
arm_tune_xscale = (tune_flags & TF_XSCALE) != 0;
- arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT);
- arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2);
- arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV);
- arm_arch_arm_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARM_DIV);
- arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE);
arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0;
- arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32);
- arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE);
arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0;
- arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST);
- if (arm_fp16_inst)
- {
- if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE)
- error ("selected fp16 options are incompatible.");
- arm_fp16_format = ARM_FP16_FORMAT_IEEE;
- }
+
+ /* And finally, set up some quirks. */
+ arm_arch_no_volatile_ce
+ = bitmap_bit_p (arm_active_target.isa, isa_quirk_no_volatile_ce);
+ arm_arch6kz
+ = arm_arch6k && bitmap_bit_p (arm_active_target.isa, isa_quirk_ARMv6kz);
/* V5 code we generate is completely interworking capable, so we turn off
TARGET_INTERWORK here to avoid many tests later on. */
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 928fad4..6661314 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -252,8 +252,7 @@ extern tree arm_fp16_type_node;
|| (arm_arch8 && !arm_arch_notm))
/* Nonzero if this chip supports LPAE. */
-#define TARGET_HAVE_LPAE \
- (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE))
+#define TARGET_HAVE_LPAE (arm_arch7ve)
/* Nonzero if this chip supports ldrex{bh} and strex{bh}. */
#define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 11/21] [arm] Delete unused arm_fp_model.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (4 preceding siblings ...)
2016-12-15 16:06 ` [PATCH 08/21] [arm] Remove insn_flags Richard Earnshaw (lists)
@ 2016-12-15 16:06 ` Richard Earnshaw (lists)
2016-12-15 16:06 ` [PATCH 04/21] [arm] Use arm_active_target for architecture and tune operations Richard Earnshaw (lists)
` (14 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:06 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 289 bytes --]
The arm_fp_model enumeration type has only had one useful value since
the FPA support was removed, and it's no-longer used anywhere. This
patch just cleans that up by removing it.
* arm.h (arm_fp_model): Delete.
---
gcc/config/arm/arm.h | 8 --------
1 file changed, 8 deletions(-)
[-- Attachment #2: 0011-arm-Delete-unused-arm_fp_model.patch --]
[-- Type: text/x-patch, Size: 510 bytes --]
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 6661314..7690e70 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -340,14 +340,6 @@ typedef unsigned long arm_fpu_feature_set;
#define FPU_FL_FP16 (1 << 1) /* Half-precision. */
#define FPU_FL_CRYPTO (1 << 2) /* Crypto extensions. */
-/* Which floating point model to use. */
-enum arm_fp_model
-{
- ARM_FP_MODEL_UNKNOWN,
- /* VFP floating point model. */
- ARM_FP_MODEL_VFP
-};
-
enum vfp_reg_type
{
VFP_NONE = 0,
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 04/21] [arm] Use arm_active_target for architecture and tune operations.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (5 preceding siblings ...)
2016-12-15 16:06 ` [PATCH 11/21] [arm] Delete unused arm_fp_model Richard Earnshaw (lists)
@ 2016-12-15 16:06 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 18/21] [arm] Use cl_target_options for configuring the active target Richard Earnshaw (lists)
` (13 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:06 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 683 bytes --]
We now start to make more use of the new data structure. This allows
us to eliminate two of the existing static variables,
arm_selected_arch and arm_selected tune.
* arm.c (arm_selected_tune): Delete static variable.
(arm_selected_arch): Likewise.
(arm_configure_build_target): Declare local versions of arm_selected
target and arm_selected_arch. Initialize more fields in target
data structure.
(arm_option_override): Use arm_active_target instead of
arm_selected_tune and arm_selected_arch.
(asm_file_start): Use arm_active_target.
---
gcc/config/arm/arm.c | 58
+++++++++++++++++++++++++++++++++++++---------------
1 file changed, 41 insertions(+), 17 deletions(-)
[-- Attachment #2: 0004-arm-Use-arm_active_target-for-architecture-and-tune-.patch --]
[-- Type: text/x-patch, Size: 5075 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index deab528..a4d370c 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2319,9 +2319,7 @@ static const struct processors all_architectures[] =
/* These are populated as commandline arguments are processed, or NULL
if not specified. */
-static const struct processors *arm_selected_arch;
static const struct processors *arm_selected_cpu;
-static const struct processors *arm_selected_tune;
/* The name of the preprocessor macro to define for this architecture. PROFILE
is replaced by the architecture name (eg. 8A) in arm_option_override () and
@@ -3068,9 +3066,10 @@ arm_configure_build_target (struct arm_build_target *target,
struct gcc_options *opts_set,
bool warn_compatible)
{
- arm_selected_arch = NULL;
+ const struct processors *arm_selected_tune = NULL;
+ const struct processors *arm_selected_arch = NULL;
+
arm_selected_cpu = NULL;
- arm_selected_tune = NULL;
bitmap_clear (target->isa);
target->core_name = NULL;
@@ -3119,17 +3118,24 @@ arm_configure_build_target (struct arm_build_target *target,
Prefer the CPU setting. */
arm_selected_arch = NULL;
}
+
+ target->core_name = arm_selected_cpu->name;
}
else
{
/* Pick a CPU based on the architecture. */
arm_selected_cpu = arm_selected_arch;
target->arch_name = arm_selected_arch->name;
+ /* Note: target->core_name is left unset in this path. */
}
}
-
+ else if (arm_selected_cpu)
+ {
+ target->core_name = arm_selected_cpu->name;
+ arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits);
+ }
/* If the user did not specify a processor, choose one for them. */
- if (!arm_selected_cpu)
+ else
{
const struct processors * sel;
auto_sbitmap sought_isa (isa_num_bits);
@@ -3229,16 +3235,27 @@ arm_configure_build_target (struct arm_build_target *target,
}
arm_selected_cpu = sel;
}
+
+ /* Now we know the CPU, we can finally initialize the target
+ structure. */
+ target->core_name = arm_selected_cpu->name;
+ arm_initialize_isa (target->isa, arm_selected_cpu->isa_bits);
}
gcc_assert (arm_selected_cpu);
+
/* The selected cpu may be an architecture, so lookup tuning by core ID. */
if (!arm_selected_tune)
arm_selected_tune = &all_cores[arm_selected_cpu->core];
+ /* Finish initializing the target structure. */
target->arch_pp_name = arm_selected_cpu->arch;
+ target->base_arch = arm_selected_cpu->base_arch;
+ target->arch_core = arm_selected_cpu->core;
+
target->tune_flags = arm_selected_tune->tune_flags;
target->tune = arm_selected_tune->tune;
+ target->tune_core = arm_selected_tune->core;
}
/* Fix up any incompatible options that the user has specified. */
@@ -3263,9 +3280,9 @@ arm_option_override (void)
insn_flags = arm_selected_cpu->flags;
arm_base_arch = arm_selected_cpu->base_arch;
- arm_tune = arm_selected_tune->core;
- tune_flags = arm_selected_tune->tune_flags;
- current_tune = arm_selected_tune->tune;
+ arm_tune = arm_active_target.tune_core;
+ tune_flags = arm_active_target.tune_flags;
+ current_tune = arm_active_target.tune;
/* TBD: Dwarf info for apcs frame is not handled yet. */
if (TARGET_APCS_FRAME)
@@ -25957,10 +25974,16 @@ arm_file_start (void)
if (TARGET_BPABI)
{
- if (arm_selected_arch)
+ /* We don't have a specified CPU. Use the architecture to
+ generate the tags.
+
+ Note: it might be better to do this unconditionally, then the
+ assembler would not need to know about all new CPU names as
+ they are added. */
+ if (!arm_active_target.core_name)
{
/* armv7ve doesn't support any extensions. */
- if (strcmp (arm_selected_arch->name, "armv7ve") == 0)
+ if (strcmp (arm_active_target.arch_name, "armv7ve") == 0)
{
/* Keep backward compatability for assemblers
which don't support armv7ve. */
@@ -25972,20 +25995,21 @@ arm_file_start (void)
}
else
{
- const char* pos = strchr (arm_selected_arch->name, '+');
+ const char* pos = strchr (arm_active_target.arch_name, '+');
if (pos)
{
char buf[32];
- gcc_assert (strlen (arm_selected_arch->name)
+ gcc_assert (strlen (arm_active_target.arch_name)
<= sizeof (buf) / sizeof (*pos));
- strncpy (buf, arm_selected_arch->name,
- (pos - arm_selected_arch->name) * sizeof (*pos));
- buf[pos - arm_selected_arch->name] = '\0';
+ strncpy (buf, arm_active_target.arch_name,
+ (pos - arm_active_target.arch_name) * sizeof (*pos));
+ buf[pos - arm_active_target.arch_name] = '\0';
asm_fprintf (asm_out_file, "\t.arch %s\n", buf);
asm_fprintf (asm_out_file, "\t.arch_extension %s\n", pos + 1);
}
else
- asm_fprintf (asm_out_file, "\t.arch %s\n", arm_selected_arch->name);
+ asm_fprintf (asm_out_file, "\t.arch %s\n",
+ arm_active_target.arch_name);
}
}
else if (strncmp (arm_selected_cpu->name, "generic", 7) == 0)
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 18/21] [arm] Use cl_target_options for configuring the active target.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (6 preceding siblings ...)
2016-12-15 16:06 ` [PATCH 04/21] [arm] Use arm_active_target for architecture and tune operations Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 12/21] [arm] Eliminate vfp_reg_type Richard Earnshaw (lists)
` (12 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1205 bytes --]
It now becomes apparent that it would be better to use the the
cl_target_options as the basis for calling arm_configure_build_target;
it already contains exactly the same fields that we need. I chose not
to rewrite the earlier patches as that would make the progression of
changes seem less logical than it currently is, with several early
changes having no immediate justification.
* arm-protos.h (arm_configure_build_target): Change second argument
to cl_target_options.
* arm.c (arm_configure_build_target): Likewise.
(arm_option_restore): Update accordingly.
(arm_option_override): Create the target_option_default_node before
calling arm_configure_build_target. Use it in call of latter.
Resynchronize after all other overrides have been calculated.
(arm_valid_target_attribute_tree): Use the target options for
reconfiguration. Resynchronize after performing override checks.
* arm-c.c (arm_pragma_target_parse): Use target optiosn from cur_tree
to reconfigure the build target.
---
gcc/config/arm/arm-c.c | 3 ++-
gcc/config/arm/arm-protos.h | 2 +-
gcc/config/arm/arm.c | 36 ++++++++++++++++++++++++------------
3 files changed, 27 insertions(+), 14 deletions(-)
[-- Attachment #2: 0018-arm-Use-cl_target_options-for-configuring-the-active.patch --]
[-- Type: text/x-patch, Size: 4507 bytes --]
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 9dd9a8d..b57af69 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -243,7 +243,8 @@ arm_pragma_target_parse (tree args, tree pop_target)
/* handle_pragma_pop_options and handle_pragma_reset_options will set
target_option_current_node, but not handle_pragma_target. */
target_option_current_node = cur_tree;
- arm_configure_build_target (&arm_active_target, &global_options,
+ arm_configure_build_target (&arm_active_target,
+ TREE_TARGET_OPTION (cur_tree),
&global_options_set, false);
}
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index da3484f..d418ca9 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -225,7 +225,7 @@ extern bool arm_change_mode_p (tree);
extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
struct gcc_options *);
extern void arm_configure_build_target (struct arm_build_target *,
- struct gcc_options *,
+ struct cl_target_option *,
struct gcc_options *, bool);
extern void arm_pr_long_calls (struct cpp_reader *);
extern void arm_pr_no_long_calls (struct cpp_reader *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 676c78b..df520e5 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2936,16 +2936,17 @@ arm_override_options_after_change_1 (struct gcc_options *opts)
static void
arm_override_options_after_change (void)
{
- arm_configure_build_target (&arm_active_target, &global_options,
+ arm_configure_build_target (&arm_active_target,
+ TREE_TARGET_OPTION (target_option_default_node),
&global_options_set, false);
arm_override_options_after_change_1 (&global_options);
}
static void
-arm_option_restore (struct gcc_options *opts, struct cl_target_option *ptr)
+arm_option_restore (struct gcc_options *, struct cl_target_option *ptr)
{
- arm_configure_build_target (&arm_active_target, opts, &global_options_set,
+ arm_configure_build_target (&arm_active_target, ptr, &global_options_set,
false);
}
@@ -3070,7 +3071,7 @@ static sbitmap isa_quirkbits;
architecture have been specified, but the two are not identical. */
void
arm_configure_build_target (struct arm_build_target *target,
- struct gcc_options *opts,
+ struct cl_target_option *opts,
struct gcc_options *opts_set,
bool warn_compatible)
{
@@ -3306,7 +3307,13 @@ arm_option_override (void)
gcc_assert (ok);
}
- arm_configure_build_target (&arm_active_target, &global_options,
+ /* Create the default target_options structure. We need this early
+ to configure the overall build target. */
+ target_option_default_node = target_option_current_node
+ = build_target_option_node (&global_options);
+
+ arm_configure_build_target (&arm_active_target,
+ TREE_TARGET_OPTION (target_option_default_node),
&global_options_set, true);
#ifdef SUBTARGET_OVERRIDE_OPTIONS
@@ -3657,14 +3664,12 @@ arm_option_override (void)
arm_option_check_internal (&global_options);
arm_option_params_internal ();
+ /* Resynchronize the saved target options. */
+ cl_target_option_save (TREE_TARGET_OPTION (target_option_default_node),
+ &global_options);
/* Register global variables with the garbage collector. */
arm_add_gc_roots ();
- /* Save the initial options in case the user does function specific
- options or #pragma target. */
- target_option_default_node = target_option_current_node
- = build_target_option_node (&global_options);
-
/* Init initial mode for testing. */
thumb_flipper = TARGET_THUMB;
}
@@ -30326,15 +30331,22 @@ tree
arm_valid_target_attribute_tree (tree args, struct gcc_options *opts,
struct gcc_options *opts_set)
{
+ tree t;
+
if (!arm_valid_target_attribute_rec (args, opts))
return NULL_TREE;
- arm_configure_build_target (&arm_active_target, opts, opts_set, false);
+ t = build_target_option_node (opts);
+ arm_configure_build_target (&arm_active_target, TREE_TARGET_OPTION (t),
+ opts_set, false);
arm_option_check_internal (opts);
/* Do any overrides, such as global options arch=xxx. */
arm_option_override_internal (opts, opts_set);
- return build_target_option_node (opts);
+ /* Resynchronize the saved target options. */
+ cl_target_option_save (TREE_TARGET_OPTION (t), opts);
+
+ return t;
}
static void
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 12/21] [arm] Eliminate vfp_reg_type
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (7 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 18/21] [arm] Use cl_target_options for configuring the active target Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 14/21] [arm] Add isa features to FPU descriptions Richard Earnshaw (lists)
` (11 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1115 bytes --]
Remove the VFP_REGS field by converting its meanings into flag
attributes. The new flag attributes build on each other describing
increasing capabilities. This allows us to do a better job when
inlining functions with differing requiremetns on the fpu environment:
we can now inline A into B if B has at least the same register set
properties as B (previously we required identical register set
properties).
* arm.h (vfp_reg_type): Delete.
(TARGET_FPU_REGS): Delete.
(arm_fpu_desc): Delete regs field.
(FPU_FL_NONE, FPU_FL_NEON, FPU_FL_FP16, FPU_FL_CRYPTO): Use unsigned
values.
(FPU_FL_DBL, FPU_FL_D32): Define.
(TARGET_VFPD32): Use feature test.
(TARGET_VFP_SINGLE): Likewise.
(TARGET_VFP_DOUBLE): Likewise.
* arm-fpus.def: Update all entries for new feature bits.
* arm.c (all_fpus): Update initializer macro.
(arm_can_inline_p): Remove test on fpu regs.
---
gcc/config/arm/arm-fpus.def | 44
++++++++++++++++++++++----------------------
gcc/config/arm/arm.c | 8 ++------
gcc/config/arm/arm.h | 26 +++++++++-----------------
3 files changed, 33 insertions(+), 45 deletions(-)
[-- Attachment #2: 0012-arm-Eliminate-vfp_reg_type.patch --]
[-- Type: text/x-patch, Size: 6099 bytes --]
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
index 04b2ef1..eca03bb 100644
--- a/gcc/config/arm/arm-fpus.def
+++ b/gcc/config/arm/arm-fpus.def
@@ -19,31 +19,31 @@
/* Before using #include to read this file, define a macro:
- ARM_FPU(NAME, REV, VFP_REGS, FEATURES)
+ ARM_FPU(NAME, REV, FEATURES)
The arguments are the fields of struct arm_fpu_desc.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_FPU("vfp", 2, VFP_REG_D16, FPU_FL_NONE)
-ARM_FPU("vfpv2", 2, VFP_REG_D16, FPU_FL_NONE)
-ARM_FPU("vfpv3", 3, VFP_REG_D32, FPU_FL_NONE)
-ARM_FPU("vfpv3-fp16", 3, VFP_REG_D32, FPU_FL_FP16)
-ARM_FPU("vfpv3-d16", 3, VFP_REG_D16, FPU_FL_NONE)
-ARM_FPU("vfpv3-d16-fp16", 3, VFP_REG_D16, FPU_FL_FP16)
-ARM_FPU("vfpv3xd", 3, VFP_REG_SINGLE, FPU_FL_NONE)
-ARM_FPU("vfpv3xd-fp16", 3, VFP_REG_SINGLE, FPU_FL_FP16)
-ARM_FPU("neon", 3, VFP_REG_D32, FPU_FL_NEON)
-ARM_FPU("neon-vfpv3", 3, VFP_REG_D32, FPU_FL_NEON)
-ARM_FPU("neon-fp16", 3, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
-ARM_FPU("vfpv4", 4, VFP_REG_D32, FPU_FL_FP16)
-ARM_FPU("vfpv4-d16", 4, VFP_REG_D16, FPU_FL_FP16)
-ARM_FPU("fpv4-sp-d16", 4, VFP_REG_SINGLE, FPU_FL_FP16)
-ARM_FPU("fpv5-sp-d16", 5, VFP_REG_SINGLE, FPU_FL_FP16)
-ARM_FPU("fpv5-d16", 5, VFP_REG_D16, FPU_FL_FP16)
-ARM_FPU("neon-vfpv4", 4, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
-ARM_FPU("fp-armv8", 8, VFP_REG_D32, FPU_FL_FP16)
-ARM_FPU("neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16)
-ARM_FPU("crypto-neon-fp-armv8", 8, VFP_REG_D32, FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
+ARM_FPU("vfp", 2, FPU_FL_DBL)
+ARM_FPU("vfpv2", 2, FPU_FL_DBL)
+ARM_FPU("vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL)
+ARM_FPU("vfpv3-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
+ARM_FPU("vfpv3-d16", 3, FPU_FL_DBL)
+ARM_FPU("vfpv3-d16-fp16", 3, FPU_FL_DBL | FPU_FL_FP16)
+ARM_FPU("vfpv3xd", 3, FPU_FL_NONE)
+ARM_FPU("vfpv3xd-fp16", 3, FPU_FL_FP16)
+ARM_FPU("neon", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON)
+ARM_FPU("neon-vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON)
+ARM_FPU("neon-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
+ARM_FPU("vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
+ARM_FPU("vfpv4-d16", 4, FPU_FL_DBL | FPU_FL_FP16)
+ARM_FPU("fpv4-sp-d16", 4, FPU_FL_FP16)
+ARM_FPU("fpv5-sp-d16", 5, FPU_FL_FP16)
+ARM_FPU("fpv5-d16", 5, FPU_FL_DBL | FPU_FL_FP16)
+ARM_FPU("neon-vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
+ARM_FPU("fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
+ARM_FPU("neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
+ARM_FPU("crypto-neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
/* Compatibility aliases. */
-ARM_FPU("vfp3", 3, VFP_REG_D32, FPU_FL_NONE)
+ARM_FPU("vfp3", 3, FPU_FL_D32 | FPU_FL_DBL)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 822ef14..820a6ab 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2323,8 +2323,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
const struct arm_fpu_desc all_fpus[] =
{
-#define ARM_FPU(NAME, REV, VFP_REGS, FEATURES) \
- { NAME, REV, VFP_REGS, FEATURES },
+#define ARM_FPU(NAME, REV, FEATURES) \
+ { NAME, REV, FEATURES },
#include "arm-fpus.def"
#undef ARM_FPU
};
@@ -30218,10 +30218,6 @@ arm_can_inline_p (tree caller, tree callee)
if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features)
return false;
- /* Need same FPU regs. */
- if (callee_fpu->regs != callee_fpu->regs)
- return false;
-
/* OK to inline between different modes.
Function with mode specific instructions, e.g using asm,
must be explicitly protected with noinline. */
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 7690e70..a412fb1 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -161,7 +161,7 @@ extern tree arm_fp16_type_node;
to be more careful with TARGET_NEON as noted below. */
/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
-#define TARGET_VFPD32 (TARGET_FPU_REGS == VFP_REG_D32)
+#define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32)
/* FPU supports VFPv3 instructions. */
#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
@@ -170,10 +170,10 @@ extern tree arm_fp16_type_node;
#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
/* FPU only supports VFP single-precision instructions. */
-#define TARGET_VFP_SINGLE (TARGET_FPU_REGS == VFP_REG_SINGLE)
+#define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0)
/* FPU supports VFP double-precision instructions. */
-#define TARGET_VFP_DOUBLE (TARGET_FPU_REGS != VFP_REG_SINGLE)
+#define TARGET_VFP_DOUBLE (TARGET_FPU_FEATURES & FPU_FL_DBL)
/* FPU supports half-precision floating-point with NEON element load/store. */
#define TARGET_NEON_FP16 \
@@ -335,24 +335,17 @@ typedef unsigned long arm_fpu_feature_set;
#define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F))
/* FPU Features. */
-#define FPU_FL_NONE (0)
-#define FPU_FL_NEON (1 << 0) /* NEON instructions. */
-#define FPU_FL_FP16 (1 << 1) /* Half-precision. */
-#define FPU_FL_CRYPTO (1 << 2) /* Crypto extensions. */
-
-enum vfp_reg_type
-{
- VFP_NONE = 0,
- VFP_REG_D16,
- VFP_REG_D32,
- VFP_REG_SINGLE
-};
+#define FPU_FL_NONE (0u)
+#define FPU_FL_NEON (1u << 0) /* NEON instructions. */
+#define FPU_FL_FP16 (1u << 1) /* Half-precision. */
+#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */
+#define FPU_FL_DBL (1u << 3) /* Has double precision. */
+#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */
extern const struct arm_fpu_desc
{
const char *name;
int rev;
- enum vfp_reg_type regs;
arm_fpu_feature_set features;
} all_fpus[];
@@ -360,7 +353,6 @@ extern const struct arm_fpu_desc
#define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name)
#define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev)
-#define TARGET_FPU_REGS (all_fpus[arm_fpu_index].regs)
#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
/* Which floating point hardware to schedule for. */
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 14/21] [arm] Add isa features to FPU descriptions
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (8 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 12/21] [arm] Eliminate vfp_reg_type Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 19/21] [arm] Use ISA feature sets for determining inlinability Richard Earnshaw (lists)
` (10 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1090 bytes --]
Similar to the new CPU and architecture ISA feature lists, we now add
similar capabilities to each FPU description. We don't use these yet,
that will come in later patches. These follow the same style as the
newly modified flag sets, but use slightly different defaults that
more accurately reflect the ISA specifications.
* arm-isa.h (isa_feature): Add bits for VFPv4, FPv5, fp16conv,
fP_dbl, fp_d32 and fp_crypto.
(ISA_ALL_FPU): Add all the new bits.
(ISA_VFPv2, ISA_VFPv3, ISA_VFPv4, ISA_FPv5): New macros.
(ISA_FP_ARMv8, ISA_FP_DBL, ISA_FP_D32, ISA_NEON, ISA_CRYPTO): Likewise.
* arm-fpus.def: Add ISA features to all FPUs.
* arm.h: (arm_fpu_desc): Add new field for ISA bits.
* arm.c (all_fpus): Initialize it.
* arm-tables.opt: Regenerated.
---
gcc/config/arm/arm-fpus.def | 44
+++++++++++++++++++++----------------------
gcc/config/arm/arm-isa.h | 30 +++++++++++++++++++++++++----
gcc/config/arm/arm-tables.opt | 10 +++++-----
gcc/config/arm/arm.c | 4 ++--
gcc/config/arm/arm.h | 1 +
5 files changed, 56 insertions(+), 33 deletions(-)
[-- Attachment #2: 0014-arm-Add-isa-features-to-FPU-descriptions.patch --]
[-- Type: text/x-patch, Size: 7531 bytes --]
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
index 25e2ebd..1be718f 100644
--- a/gcc/config/arm/arm-fpus.def
+++ b/gcc/config/arm/arm-fpus.def
@@ -19,31 +19,31 @@
/* Before using #include to read this file, define a macro:
- ARM_FPU(NAME, FEATURES)
+ ARM_FPU(NAME, ISA, FEATURES)
The arguments are the fields of struct arm_fpu_desc.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_FPU("vfp", FPU_VFPv2 | FPU_DBL)
-ARM_FPU("vfpv2", FPU_VFPv2 | FPU_DBL)
-ARM_FPU("vfpv3", FPU_VFPv3 | FPU_D32)
-ARM_FPU("vfpv3-fp16", FPU_VFPv3 | FPU_D32 | FPU_FP16)
-ARM_FPU("vfpv3-d16", FPU_VFPv3 | FPU_DBL)
-ARM_FPU("vfpv3-d16-fp16", FPU_VFPv3 | FPU_DBL | FPU_FP16)
-ARM_FPU("vfpv3xd", FPU_VFPv3)
-ARM_FPU("vfpv3xd-fp16", FPU_VFPv3 | FPU_FP16)
-ARM_FPU("neon", FPU_VFPv3 | FPU_NEON)
-ARM_FPU("neon-vfpv3", FPU_VFPv3 | FPU_NEON)
-ARM_FPU("neon-fp16", FPU_VFPv3 | FPU_NEON | FPU_FP16)
-ARM_FPU("vfpv4", FPU_VFPv4 | FPU_D32 | FPU_FP16)
-ARM_FPU("vfpv4-d16", FPU_VFPv4 | FPU_DBL | FPU_FP16)
-ARM_FPU("fpv4-sp-d16", FPU_VFPv4 | FPU_FP16)
-ARM_FPU("fpv5-sp-d16", FPU_VFPv5 | FPU_FP16)
-ARM_FPU("fpv5-d16", FPU_VFPv5 | FPU_DBL | FPU_FP16)
-ARM_FPU("neon-vfpv4", FPU_VFPv4 | FPU_NEON | FPU_FP16)
-ARM_FPU("fp-armv8", FPU_ARMv8 | FPU_D32 | FPU_FP16)
-ARM_FPU("neon-fp-armv8", FPU_ARMv8 | FPU_NEON | FPU_FP16)
-ARM_FPU("crypto-neon-fp-armv8", FPU_ARMv8 | FPU_CRYPTO | FPU_FP16)
+ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL)
+ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL)
+ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32)
+ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_D32 | FPU_FP16)
+ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL), FPU_VFPv3 | FPU_DBL)
+ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_DBL | FPU_FP16)
+ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3), FPU_VFPv3)
+ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_FP16)
+ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON)
+ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON)
+ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_NEON | FPU_FP16)
+ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32), FPU_VFPv4 | FPU_D32 | FPU_FP16)
+ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON), FPU_VFPv4 | FPU_NEON | FPU_FP16)
+ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL), FPU_VFPv4 | FPU_DBL | FPU_FP16)
+ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4), FPU_VFPv4 | FPU_FP16)
+ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5), FPU_VFPv5 | FPU_FP16)
+ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL), FPU_VFPv5 | FPU_DBL | FPU_FP16)
+ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32), FPU_ARMv8 | FPU_D32 | FPU_FP16)
+ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON), FPU_ARMv8 | FPU_NEON | FPU_FP16)
+ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO), FPU_ARMv8 | FPU_CRYPTO | FPU_FP16)
/* Compatibility aliases. */
-ARM_FPU("vfp3", FPU_VFPv3 | FPU_D32)
+ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32)
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index 2d47c1b..25182e52 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -53,10 +53,18 @@ enum isa_feature
isa_bit_ARMv8_2, /* Architecutre rel 8.2. */
isa_bit_cmse, /* M-Profile security extensions. */
/* Floating point and Neon extensions. */
- isa_bit_VFPv2, /* Vector floating point v2 (our base level). */
+ /* VFPv1 is not supported in GCC. */
+ isa_bit_VFPv2, /* Vector floating point v2. */
isa_bit_VFPv3, /* Vector floating point v3. */
+ isa_bit_VFPv4, /* Vector floating point v4. */
+ isa_bit_FPv5, /* Floating point v5. */
+ isa_bit_FP_ARMv8, /* ARMv8 floating-point extension. */
isa_bit_neon, /* Advanced SIMD instructions. */
- isa_bit_fp16, /* FP16 extension (half-precision float). */
+ isa_bit_fp16conv, /* Conversions to/from fp16 (VFPv3 extension). */
+ isa_bit_fp_dbl, /* Double precision operations supported. */
+ isa_bit_fp_d32, /* 32 Double precision registers. */
+ isa_bit_crypto, /* Crypto extension to ARMv8. */
+ isa_bit_fp16, /* FP16 data processing (half-precision float). */
/* ISA Quirks (errata?). Don't forget to add this to the list of
all quirks below. */
@@ -119,8 +127,22 @@ enum isa_feature
#define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
/* List of all FPU bits to strip out if -mfpu is used to override the
- default. */
-#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_neon
+ default. isa_bit_fp16 is deliberately missing from this list. */
+#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, \
+ isa_bit_FPv5, isa_bit_FP_ARMv8, isa_bit_neon, isa_bit_fp16conv, \
+ isa_bit_fp_dbl, isa_bit_fp_d32, isa_bit_crypto
+
+/* Useful combinations. */
+#define ISA_VFPv2 isa_bit_VFPv2
+#define ISA_VFPv3 ISA_VFPv2, isa_bit_VFPv3
+#define ISA_VFPv4 ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv
+#define ISA_FPv5 ISA_VFPv4, isa_bit_FPv5
+#define ISA_FP_ARMv8 ISA_FPv5, isa_bit_FP_ARMv8
+
+#define ISA_FP_DBL isa_bit_fp_dbl
+#define ISA_FP_D32 ISA_FP_DBL, isa_bit_fp_d32
+#define ISA_NEON ISA_FP_D32, isa_bit_neon
+#define ISA_CRYPTO ISA_NEON, isa_bit_crypto
/* List of all quirk bits to strip out when comparing CPU features with
architectures. */
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 9d83379..faa00aa 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -504,19 +504,19 @@ EnumValue
Enum(arm_fpu) String(vfpv4) Value(11)
EnumValue
-Enum(arm_fpu) String(vfpv4-d16) Value(12)
+Enum(arm_fpu) String(neon-vfpv4) Value(12)
EnumValue
-Enum(arm_fpu) String(fpv4-sp-d16) Value(13)
+Enum(arm_fpu) String(vfpv4-d16) Value(13)
EnumValue
-Enum(arm_fpu) String(fpv5-sp-d16) Value(14)
+Enum(arm_fpu) String(fpv4-sp-d16) Value(14)
EnumValue
-Enum(arm_fpu) String(fpv5-d16) Value(15)
+Enum(arm_fpu) String(fpv5-sp-d16) Value(15)
EnumValue
-Enum(arm_fpu) String(neon-vfpv4) Value(16)
+Enum(arm_fpu) String(fpv5-d16) Value(16)
EnumValue
Enum(arm_fpu) String(fp-armv8) Value(17)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index e555cf6..bc246c9 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2323,8 +2323,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
const struct arm_fpu_desc all_fpus[] =
{
-#define ARM_FPU(NAME, FEATURES) \
- { NAME, FEATURES },
+#define ARM_FPU(NAME, ISA, FEATURES) \
+ { NAME, {ISA isa_nobit}, FEATURES },
#include "arm-fpus.def"
#undef ARM_FPU
};
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 332f0fa..908e763 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -363,6 +363,7 @@ typedef unsigned long arm_fpu_feature_set;
extern const struct arm_fpu_desc
{
const char *name;
+ enum isa_feature isa_bits[isa_num_bits];
arm_fpu_feature_set features;
} all_fpus[];
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 19/21] [arm] Use ISA feature sets for determining inlinability.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (9 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 14/21] [arm] Add isa features to FPU descriptions Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 15/21] [arm] Initialize fpu capability bits in arm_active_target Richard Earnshaw (lists)
` (9 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 380 bytes --]
Now that we can construct the build target isa from the cl_target_options
data we can use this to determine inlinability. This eliminates the
final remaining use of the FPU features field.
* arm.c (arm_can_inline_p): Use ISA features for determining
inlinability.
---
gcc/config/arm/arm.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
[-- Attachment #2: 0019-arm-Use-ISA-feature-sets-for-determining-inlinabilit.patch --]
[-- Type: text/x-patch, Size: 1916 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index df520e5..1d3bb89 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -30227,6 +30227,7 @@ arm_can_inline_p (tree caller, tree callee)
{
tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller);
tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee);
+ bool can_inline = true;
struct cl_target_option *caller_opts
= TREE_TARGET_OPTION (caller_tree ? caller_tree
@@ -30236,19 +30237,29 @@ arm_can_inline_p (tree caller, tree callee)
= TREE_TARGET_OPTION (callee_tree ? callee_tree
: target_option_default_node);
- const struct arm_fpu_desc *caller_fpu
- = &all_fpus[caller_opts->x_arm_fpu_index];
- const struct arm_fpu_desc *callee_fpu
- = &all_fpus[callee_opts->x_arm_fpu_index];
+ if (callee_opts == caller_opts)
+ return true;
- /* Callee's fpu features should be a subset of the caller's. */
- if ((caller_fpu->features & callee_fpu->features) != callee_fpu->features)
- return false;
+ /* Callee's ISA features should be a subset of the caller's. */
+ struct arm_build_target caller_target;
+ struct arm_build_target callee_target;
+ caller_target.isa = sbitmap_alloc (isa_num_bits);
+ callee_target.isa = sbitmap_alloc (isa_num_bits);
+
+ arm_configure_build_target (&caller_target, caller_opts, &global_options_set,
+ false);
+ arm_configure_build_target (&callee_target, callee_opts, &global_options_set,
+ false);
+ if (!bitmap_subset_p (callee_target.isa, caller_target.isa))
+ can_inline = false;
+
+ sbitmap_free (caller_target.isa);
+ sbitmap_free (callee_target.isa);
/* OK to inline between different modes.
Function with mode specific instructions, e.g using asm,
must be explicitly protected with noinline. */
- return true;
+ return can_inline;
}
/* Hook to fix function's alignment affected by target attribute. */
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 15/21] [arm] Initialize fpu capability bits in arm_active_target.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (10 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 19/21] [arm] Use ISA feature sets for determining inlinability Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 07/21] [arm] Use arm_active_target when configuring builtins Richard Earnshaw (lists)
` (8 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1470 bytes --]
Now that we can describe the FPU with the standard ISA bits we need to
initialize them. However, the FPU settings can be changed with target build
attributes, so we also need to reset them if things change. This requires
a bit of juggling about with the existing code to ensure that the active
target is reconfigured after each change to the target options.
* arm-protos.h: Include sbitmap.h
(arm_configure_build_target): Make public.
* arm.c (arm_configure_build_target): Now not static.
(arm_valid_target_attribute_rec): Move internal option check to...
(arm_valid_target_attribute_tree0: ... here. Also reconfingure the
active target.
(arm_override_options_after_change): Call arm_configure_build_target.
(isa_all_fpubits): Renamed from isa_fpubits.
(arm_option_restore): New function.
(TARGET_OPTION_RESTORE): Register it.
(arm_configure_build_target): Initialize the FPU capability bits in
the isa.
(arm_option_override): Move the code that forces the setting of the
FPU option before the call to arm_configure_build_target.
* arm.opt (march): Mark as Save.
(mcpu, mtune): Likewise.
* arm-c.c (arm_pragma_target_parse): Reconfigure the build target
after pragmas change the target options.
---
gcc/config/arm/arm-c.c | 2 ++
gcc/config/arm/arm-protos.h | 4 +++
gcc/config/arm/arm.c | 69
++++++++++++++++++++++++++++++---------------
gcc/config/arm/arm.opt | 6 ++--
4 files changed, 55 insertions(+), 26 deletions(-)
[-- Attachment #2: 0015-arm-Initialize-fpu-capability-bits-in-arm_active_tar.patch --]
[-- Type: text/x-patch, Size: 8478 bytes --]
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index b592134..9dd9a8d 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -243,6 +243,8 @@ arm_pragma_target_parse (tree args, tree pop_target)
/* handle_pragma_pop_options and handle_pragma_reset_options will set
target_option_current_node, but not handle_pragma_target. */
target_option_current_node = cur_tree;
+ arm_configure_build_target (&arm_active_target, &global_options,
+ &global_options_set, false);
}
/* Update macros if target_node changes. The global state will be restored
diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h
index 659959b..da3484f 100644
--- a/gcc/config/arm/arm-protos.h
+++ b/gcc/config/arm/arm-protos.h
@@ -24,6 +24,7 @@
#include "arm-flags.h"
#include "arm-isa.h"
+#include "sbitmap.h"
extern enum unwind_info_type arm_except_unwind_info (struct gcc_options *);
extern int use_return_insn (int, rtx);
@@ -223,6 +224,9 @@ extern bool arm_change_mode_p (tree);
extern tree arm_valid_target_attribute_tree (tree, struct gcc_options *,
struct gcc_options *);
+extern void arm_configure_build_target (struct arm_build_target *,
+ struct gcc_options *,
+ struct gcc_options *, bool);
extern void arm_pr_long_calls (struct cpp_reader *);
extern void arm_pr_no_long_calls (struct cpp_reader *);
extern void arm_pr_long_calls_off (struct cpp_reader *);
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bc246c9..437ee2d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -231,6 +231,8 @@ static tree arm_build_builtin_va_list (void);
static void arm_expand_builtin_va_start (tree, rtx);
static tree arm_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
static void arm_option_override (void);
+static void arm_option_restore (struct gcc_options *,
+ struct cl_target_option *);
static void arm_override_options_after_change (void);
static void arm_option_print (FILE *, int, struct cl_target_option *);
static void arm_set_current_function (tree);
@@ -408,6 +410,9 @@ static const struct attribute_spec arm_attribute_table[] =
#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE arm_override_options_after_change
+#undef TARGET_OPTION_RESTORE
+#define TARGET_OPTION_RESTORE arm_option_restore
+
#undef TARGET_OPTION_PRINT
#define TARGET_OPTION_PRINT arm_option_print
@@ -2932,9 +2937,19 @@ arm_override_options_after_change_1 (struct gcc_options *opts)
static void
arm_override_options_after_change (void)
{
+ arm_configure_build_target (&arm_active_target, &global_options,
+ &global_options_set, false);
+
arm_override_options_after_change_1 (&global_options);
}
+static void
+arm_option_restore (struct gcc_options *opts, struct cl_target_option *ptr)
+{
+ arm_configure_build_target (&arm_active_target, opts, &global_options_set,
+ false);
+}
+
/* Reset options between modes that the user has specified. */
static void
arm_option_override_internal (struct gcc_options *opts,
@@ -3048,13 +3063,13 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
bitmap_set_bit (isa, *(isa_bits++));
}
-static sbitmap isa_fpubits;
+static sbitmap isa_all_fpubits;
static sbitmap isa_quirkbits;
/* Configure a build target TARGET from the user-specified options OPTS and
OPTS_SET. If WARN_COMPATIBLE, emit a diagnostic if both the CPU and
architecture have been specified, but the two are not identical. */
-static void
+void
arm_configure_build_target (struct arm_build_target *target,
struct gcc_options *opts,
struct gcc_options *opts_set,
@@ -3063,6 +3078,7 @@ arm_configure_build_target (struct arm_build_target *target,
const struct processors *arm_selected_tune = NULL;
const struct processors *arm_selected_arch = NULL;
const struct processors *arm_selected_cpu = NULL;
+ const struct arm_fpu_desc *arm_selected_fpu = NULL;
bitmap_clear (target->isa);
target->core_name = NULL;
@@ -3093,7 +3109,7 @@ arm_configure_build_target (struct arm_build_target *target,
/* Ignore any bits that are quirk bits. */
bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits);
/* Ignore (for now) any bits that might be set by -mfpu. */
- bitmap_and_compl (cpu_isa, cpu_isa, isa_fpubits);
+ bitmap_and_compl (cpu_isa, cpu_isa, isa_all_fpubits);
if (!bitmap_empty_p (cpu_isa))
{
@@ -3239,6 +3255,13 @@ arm_configure_build_target (struct arm_build_target *target,
gcc_assert (arm_selected_cpu);
+ arm_selected_fpu = &all_fpus[opts->x_arm_fpu_index];
+ auto_sbitmap fpu_bits(isa_num_bits);
+
+ arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits);
+ bitmap_and_compl (target->isa, target->isa, isa_all_fpubits);
+ bitmap_ior (target->isa, target->isa, fpu_bits);
+
/* The selected cpu may be an architecture, so lookup tuning by core ID. */
if (!arm_selected_tune)
arm_selected_tune = &all_cores[arm_selected_cpu->core];
@@ -3263,11 +3286,27 @@ arm_option_override (void)
isa_quirkbits = sbitmap_alloc (isa_num_bits);
arm_initialize_isa (isa_quirkbits, quirk_bitlist);
- isa_fpubits = sbitmap_alloc (isa_num_bits);
- arm_initialize_isa (isa_fpubits, fpu_bitlist);
+ isa_all_fpubits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_all_fpubits, fpu_bitlist);
arm_active_target.isa = sbitmap_alloc (isa_num_bits);
+ if (!global_options_set.x_arm_fpu_index)
+ {
+ const char *target_fpu_name;
+ bool ok;
+
+#ifdef FPUTYPE_DEFAULT
+ target_fpu_name = FPUTYPE_DEFAULT;
+#else
+ target_fpu_name = "vfp";
+#endif
+
+ ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
+ CL_TARGET);
+ gcc_assert (ok);
+ }
+
arm_configure_build_target (&arm_active_target, &global_options,
&global_options_set, true);
@@ -3378,22 +3417,6 @@ arm_option_override (void)
if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT)
error ("iwmmxt abi requires an iwmmxt capable cpu");
- if (!global_options_set.x_arm_fpu_index)
- {
- const char *target_fpu_name;
- bool ok;
-
-#ifdef FPUTYPE_DEFAULT
- target_fpu_name = FPUTYPE_DEFAULT;
-#else
- target_fpu_name = "vfp";
-#endif
-
- ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
- CL_TARGET);
- gcc_assert (ok);
- }
-
/* If soft-float is specified then don't use FPU. */
if (TARGET_SOFT_FLOAT)
arm_fpu_attr = FPU_NONE;
@@ -30293,8 +30316,6 @@ arm_valid_target_attribute_rec (tree args, struct gcc_options *opts)
error ("attribute(target(\"%s\")) is unknown", q);
return false;
}
-
- arm_option_check_internal (opts);
}
return true;
@@ -30309,6 +30330,8 @@ arm_valid_target_attribute_tree (tree args, struct gcc_options *opts,
if (!arm_valid_target_attribute_rec (args, opts))
return NULL_TREE;
+ arm_configure_build_target (&arm_active_target, opts, opts_set, false);
+ arm_option_check_internal (opts);
/* Do any overrides, such as global options arch=xxx. */
arm_option_override_internal (opts, opts_set);
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index a37facc..934144d 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -73,7 +73,7 @@ mapcs-stack-check
Target Report Mask(APCS_STACK) Undocumented
march=
-Target RejectNegative ToLower Joined Enum(arm_arch) Var(arm_arch_option)
+Target RejectNegative ToLower Joined Enum(arm_arch) Var(arm_arch_option) Save
Specify the name of the target architecture.
; Other arm_arch values are loaded from arm-tables.opt
@@ -98,7 +98,7 @@ Target Report Mask(CALLER_INTERWORKING)
Thumb: Assume function pointers may go to non-Thumb aware code.
mcpu=
-Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_cpu_option) Init(TARGET_CPU_arm_none)
+Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_cpu_option) Init(TARGET_CPU_arm_none) Save
Specify the name of the target CPU.
mfloat-abi=
@@ -223,7 +223,7 @@ Target Report Mask(TPCS_LEAF_FRAME)
Thumb: Generate (leaf) stack frames even if not needed.
mtune=
-Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_tune_option) Init(TARGET_CPU_arm_none)
+Target RejectNegative ToLower Joined Enum(processor_type) Var(arm_tune_option) Init(TARGET_CPU_arm_none) Save
Tune code for the given processor.
mprint-tune-info
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 07/21] [arm] Use arm_active_target when configuring builtins
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (11 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 15/21] [arm] Initialize fpu capability bits in arm_active_target Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:07 ` [PATCH 16/21] [arm] Eliminate TARGET_FPU_NAME Richard Earnshaw (lists)
` (7 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 897 bytes --]
This patch uses the new ISA data structure to determine which builtins
to add. It entirely eliminates the need for insn_flags to be a global
variable, but we're about to delete that in the following patches, so
for now we leave it as a global.
* arm-builtins.c: Include sbitmap.h.
(def_mbuiltin): Change first parameter to a flag bit. Use it to test
available features in the current target.
(struct builtin_description): Change type of feature field.
(IWMMXT_BUILTIN): Use the isa_features types.
(IWMMXT2_BUILTIN): Likewise.
(IWMMXT_BUILTIN2): Likewise.
(IWMMXT2_BUILTIN2): Likewise.
(CRC32_BUILTIN): Likewise.
(CRYPTO_BUILTIN): Likewise.
(iwmmx_builtin): Likewise.
(iwmmx2_builtin): Likewise.
(arm_iwmmxt_builtin): Check for specific feature bits.
---
gcc/config/arm/arm-builtins.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
[-- Attachment #2: 0007-arm-Use-arm_active_target-when-configuring-builtins.patch --]
[-- Type: text/x-patch, Size: 4439 bytes --]
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index 1444420..80d3b67 100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -37,6 +37,7 @@
#include "expr.h"
#include "langhooks.h"
#include "case-cfn-macros.h"
+#include "sbitmap.h"
#define SIMD_MAX_BUILTIN_ARGS 5
@@ -1154,11 +1155,11 @@ arm_init_crypto_builtins (void)
#undef NUM_DREG_TYPES
#undef NUM_QREG_TYPES
-#define def_mbuiltin(FLAGS, NAME, TYPE, CODE) \
+#define def_mbuiltin(FLAG, NAME, TYPE, CODE) \
do \
{ \
- const arm_feature_set flags = FLAGS; \
- if (ARM_FSET_CPU_SUBSET (flags, insn_flags)) \
+ if (FLAG == isa_nobit \
+ || bitmap_bit_p (arm_active_target.isa, FLAG)) \
{ \
tree bdecl; \
bdecl = add_builtin_function ((NAME), (TYPE), (CODE), \
@@ -1170,7 +1171,7 @@ arm_init_crypto_builtins (void)
struct builtin_description
{
- const arm_feature_set features;
+ const enum isa_feature feature;
const enum insn_code icode;
const char * const name;
const enum arm_builtins code;
@@ -1181,12 +1182,12 @@ struct builtin_description
static const struct builtin_description bdesc_2arg[] =
{
#define IWMMXT_BUILTIN(code, string, builtin) \
- { ARM_FSET_MAKE_CPU1 (FL_IWMMXT), CODE_FOR_##code, \
+ { isa_bit_iwmmxt, CODE_FOR_##code, \
"__builtin_arm_" string, \
ARM_BUILTIN_##builtin, UNKNOWN, 0 },
#define IWMMXT2_BUILTIN(code, string, builtin) \
- { ARM_FSET_MAKE_CPU1 (FL_IWMMXT2), CODE_FOR_##code, \
+ { isa_bit_iwmmxt2, CODE_FOR_##code, \
"__builtin_arm_" string, \
ARM_BUILTIN_##builtin, UNKNOWN, 0 },
@@ -1270,11 +1271,11 @@ static const struct builtin_description bdesc_2arg[] =
IWMMXT_BUILTIN (iwmmxt_walignr3, "walignr3", WALIGNR3)
#define IWMMXT_BUILTIN2(code, builtin) \
- { ARM_FSET_MAKE_CPU1 (FL_IWMMXT), CODE_FOR_##code, NULL, \
+ { isa_bit_iwmmxt, CODE_FOR_##code, NULL, \
ARM_BUILTIN_##builtin, UNKNOWN, 0 },
#define IWMMXT2_BUILTIN2(code, builtin) \
- { ARM_FSET_MAKE_CPU2 (FL_IWMMXT2), CODE_FOR_##code, NULL, \
+ { isa_bit_iwmmxt2, CODE_FOR_##code, NULL, \
ARM_BUILTIN_##builtin, UNKNOWN, 0 },
IWMMXT2_BUILTIN2 (iwmmxt_waddbhusm, WADDBHUSM)
@@ -1290,7 +1291,7 @@ static const struct builtin_description bdesc_2arg[] =
#define FP_BUILTIN(L, U) \
- {ARM_FSET_EMPTY, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
+ {isa_nobit, CODE_FOR_##L, "__builtin_arm_"#L, ARM_BUILTIN_##U, \
UNKNOWN, 0},
FP_BUILTIN (get_fpscr, GET_FPSCR)
@@ -1298,7 +1299,7 @@ static const struct builtin_description bdesc_2arg[] =
#undef FP_BUILTIN
#define CRC32_BUILTIN(L, U) \
- {ARM_FSET_EMPTY, CODE_FOR_##L, "__builtin_arm_"#L, \
+ {isa_nobit, CODE_FOR_##L, "__builtin_arm_"#L, \
ARM_BUILTIN_##U, UNKNOWN, 0},
CRC32_BUILTIN (crc32b, CRC32B)
CRC32_BUILTIN (crc32h, CRC32H)
@@ -1310,7 +1311,7 @@ static const struct builtin_description bdesc_2arg[] =
#define CRYPTO_BUILTIN(L, U) \
- {ARM_FSET_EMPTY, CODE_FOR_crypto_##L, "__builtin_arm_crypto_"#L, \
+ {isa_nobit, CODE_FOR_crypto_##L, "__builtin_arm_crypto_"#L, \
ARM_BUILTIN_CRYPTO_##U, UNKNOWN, 0},
#undef CRYPTO1
#undef CRYPTO2
@@ -1567,9 +1568,9 @@ arm_init_iwmmxt_builtins (void)
machine_mode mode;
tree type;
- if (d->name == 0 ||
- !(ARM_FSET_HAS_CPU1 (d->features, FL_IWMMXT) ||
- ARM_FSET_HAS_CPU1 (d->features, FL_IWMMXT2)))
+ if (d->name == 0
+ || !(d->feature == isa_bit_iwmmxt
+ || d->feature == isa_bit_iwmmxt2))
continue;
mode = insn_data[d->icode].operand[1].mode;
@@ -1593,16 +1594,16 @@ arm_init_iwmmxt_builtins (void)
gcc_unreachable ();
}
- def_mbuiltin (d->features, d->name, type, d->code);
+ def_mbuiltin (d->feature, d->name, type, d->code);
}
/* Add the remaining MMX insns with somewhat more complicated types. */
#define iwmmx_mbuiltin(NAME, TYPE, CODE) \
- def_mbuiltin (ARM_FSET_MAKE_CPU1 (FL_IWMMXT), "__builtin_arm_" NAME, \
+ def_mbuiltin (isa_bit_iwmmxt, "__builtin_arm_" NAME, \
(TYPE), ARM_BUILTIN_ ## CODE)
#define iwmmx2_mbuiltin(NAME, TYPE, CODE) \
- def_mbuiltin (ARM_FSET_MAKE_CPU1 (FL_IWMMXT2), "__builtin_arm_" NAME, \
+ def_mbuiltin (isa_bit_iwmmxt2, "__builtin_arm_" NAME, \
(TYPE), ARM_BUILTIN_ ## CODE)
iwmmx_mbuiltin ("wzero", di_ftype_void, WZERO);
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 16/21] [arm] Eliminate TARGET_FPU_NAME.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (12 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 07/21] [arm] Use arm_active_target when configuring builtins Richard Earnshaw (lists)
@ 2016-12-15 16:07 ` Richard Earnshaw (lists)
2016-12-15 16:08 ` [PATCH 06/21] [arm] Add new isa quirk bit for Cortex-M3 ldrd issue Richard Earnshaw (lists)
` (6 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:07 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 844 bytes --]
Rather than assuming a specific fpu name has been selected, we work
out the FPU from the ISA properties. This is necessary since once we
have default FPUs selected by the processor, there will be no explicit
entry in the table of fpus to refer to.
This also fixes a bug with the code I added recently to permit new
aliases for existing FPU names: the new names cannot be passed to the
assembler since it does not recognize them. By mapping the ISA
features back to the canonical names we avoid having to teach the
assembler about the new names.
* arm.h (TARGET_FPU_NAME): Delete.
* arm.c (arm_identify_fpu_from_isa): New function.
(arm_declare_function_name): Use it to get the name for the FPU.
---
gcc/config/arm/arm.c | 26 ++++++++++++++++++++++++--
gcc/config/arm/arm.h | 1 -
2 files changed, 24 insertions(+), 3 deletions(-)
[-- Attachment #2: 0016-arm-Eliminate-TARGET_FPU_NAME.patch --]
[-- Type: text/x-patch, Size: 2247 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 437ee2d..df7a3ea 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3256,7 +3256,7 @@ arm_configure_build_target (struct arm_build_target *target,
gcc_assert (arm_selected_cpu);
arm_selected_fpu = &all_fpus[opts->x_arm_fpu_index];
- auto_sbitmap fpu_bits(isa_num_bits);
+ auto_sbitmap fpu_bits (isa_num_bits);
arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits);
bitmap_and_compl (target->isa, target->isa, isa_all_fpubits);
@@ -30433,6 +30433,26 @@ arm_valid_target_attribute_p (tree fndecl, tree ARG_UNUSED (name),
return ret;
}
+/* Match an ISA feature bitmap to a named FPU. We always use the
+ first entry that exactly matches the feature set, so that we
+ effectively canonicalize the FPU name for the assembler. */
+static const char*
+arm_identify_fpu_from_isa (sbitmap isa)
+{
+ auto_sbitmap fpubits (isa_num_bits);
+ auto_sbitmap cand_fpubits (isa_num_bits);
+
+ bitmap_and (fpubits, isa, isa_all_fpubits);
+ for (unsigned int i = 0; i < ARRAY_SIZE (all_fpus); i++)
+ {
+ arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits);
+ if (bitmap_equal_p (fpubits, cand_fpubits))
+ return all_fpus[i].name;
+ }
+ /* We must find an entry, or things have gone wrong. */
+ gcc_unreachable ();
+}
+
void
arm_declare_function_name (FILE *stream, const char *name, tree decl)
{
@@ -30454,7 +30474,9 @@ arm_declare_function_name (FILE *stream, const char *name, tree decl)
fprintf (stream, "\t.arm\n");
asm_fprintf (asm_out_file, "\t.fpu %s\n",
- TARGET_SOFT_FLOAT ? "softvfp" : TARGET_FPU_NAME);
+ (TARGET_SOFT_FLOAT
+ ? "softvfp"
+ : arm_identify_fpu_from_isa (arm_active_target.isa)));
if (TARGET_POKE_FUNCTION_NAME)
arm_poke_function_name (stream, (const char *) name);
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 908e763..980bb74 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -369,7 +369,6 @@ extern const struct arm_fpu_desc
/* Accessors. */
-#define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name)
#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
/* Which floating point hardware to schedule for. */
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 06/21] [arm] Add new isa quirk bit for Cortex-M3 ldrd issue.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (13 preceding siblings ...)
2016-12-15 16:07 ` [PATCH 16/21] [arm] Eliminate TARGET_FPU_NAME Richard Earnshaw (lists)
@ 2016-12-15 16:08 ` Richard Earnshaw (lists)
2016-12-15 16:08 ` [PATCH 09/21] [arm] Rework arm-common to use new feature bits Richard Earnshaw (lists)
` (5 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:08 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 966 bytes --]
With the new data structures it is trivial to add a new field and we
aren't (too) limited as to the number we have. This patch adds a new
bit to describe the need for a particular compiler behaviour
modification: in this case a quirk in the cortex-m3.
* arm-isa.h (enum isa_feature): Add isa_quirk_cm3_ldrd.
(ISA_ALL_QUIRKS): New macro.
* arm-cores.def (cortex-m3): Add isa_quirk_cm3_ldrd to isa feature list.
* arm.c (isa_quirkbits): New feature-list bitmap.
(arm_configure_build_target): Ignore quirk bits when comparing an
architecture feature list with a CPU feature list.
(arm_option_override): Initialize_isa_quirkbits. If the user has
not specified -m[no-]fix-cortex-m3-ldrd, automatically enable the
feature if isa_quirk_cm3_ldrd appears in the isa feature list.
---
gcc/config/arm/arm-cores.def | 2 +-
gcc/config/arm/arm-isa.h | 9 ++++++++-
gcc/config/arm/arm.c | 9 ++++++++-
3 files changed, 17 insertions(+), 3 deletions(-)
[-- Attachment #2: 0006-arm-Add-new-isa-quirk-bit-for-Cortex-M3-ldrd-issue.patch --]
[-- Type: text/x-patch, Size: 4122 bytes --]
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 7c951f3..7f64a1f 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -160,7 +160,7 @@ ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv
ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
+ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
/* V7 big.LITTLE implementations */
diff --git a/gcc/config/arm/arm-isa.h b/gcc/config/arm/arm-isa.h
index 15eb6e1..2d47c1b 100644
--- a/gcc/config/arm/arm-isa.h
+++ b/gcc/config/arm/arm-isa.h
@@ -58,9 +58,11 @@ enum isa_feature
isa_bit_neon, /* Advanced SIMD instructions. */
isa_bit_fp16, /* FP16 extension (half-precision float). */
- /* ISA Quirks (errata?). */
+ /* ISA Quirks (errata?). Don't forget to add this to the list of
+ all quirks below. */
isa_quirk_no_volatile_ce, /* No volatile memory in IT blocks. */
isa_quirk_ARMv6kz, /* Previously mis-identified by GCC. */
+ isa_quirk_cm3_ldrd, /* Cortex-M3 LDRD quirk. */
/* Aren't currently, but probably should be tuning bits. */
isa_bit_smallmul, /* Slow multiply operations. */
@@ -120,6 +122,11 @@ enum isa_feature
default. */
#define ISA_ALL_FPU isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_neon
+/* List of all quirk bits to strip out when comparing CPU features with
+ architectures. */
+#define ISA_ALL_QUIRKS isa_quirk_no_volatile_ce, isa_quirk_ARMv6kz, \
+ isa_quirk_cm3_ldrd
+
/* Helper macro so that we can concatenate multiple features together
with arm-*.def files, since macro substitution can't have commas within an
argument that lacks parenthesis. */
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 3806226..c6be4d8 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -3056,6 +3056,7 @@ arm_initialize_isa (sbitmap isa, const enum isa_feature *isa_bits)
}
static sbitmap isa_fpubits;
+static sbitmap isa_quirkbits;
/* Configure a build target TARGET from the user-specified options OPTS and
OPTS_SET. If WARN_COMPATIBLE, emit a diagnostic if both the CPU and
@@ -3097,6 +3098,8 @@ arm_configure_build_target (struct arm_build_target *target,
arm_initialize_isa (cpu_isa, arm_selected_cpu->isa_bits);
bitmap_xor (cpu_isa, cpu_isa, target->isa);
+ /* Ignore any bits that are quirk bits. */
+ bitmap_and_compl (cpu_isa, cpu_isa, isa_quirkbits);
/* Ignore (for now) any bits that might be set by -mfpu. */
bitmap_and_compl (cpu_isa, cpu_isa, isa_fpubits);
@@ -3263,6 +3266,10 @@ static void
arm_option_override (void)
{
static const enum isa_feature fpu_bitlist[] = { ISA_ALL_FPU, isa_nobit };
+ static const enum isa_feature quirk_bitlist[] = { ISA_ALL_QUIRKS, isa_nobit};
+
+ isa_quirkbits = sbitmap_alloc (isa_num_bits);
+ arm_initialize_isa (isa_quirkbits, quirk_bitlist);
isa_fpubits = sbitmap_alloc (isa_num_bits);
arm_initialize_isa (isa_fpubits, fpu_bitlist);
@@ -3510,7 +3517,7 @@ arm_option_override (void)
/* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */
if (fix_cm3_ldrd == 2)
{
- if (arm_selected_cpu->core == TARGET_CPU_cortexm3)
+ if (bitmap_bit_p (arm_active_target.isa, isa_quirk_cm3_ldrd))
fix_cm3_ldrd = 1;
else
fix_cm3_ldrd = 0;
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 09/21] [arm] Rework arm-common to use new feature bits.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (14 preceding siblings ...)
2016-12-15 16:08 ` [PATCH 06/21] [arm] Add new isa quirk bit for Cortex-M3 ldrd issue Richard Earnshaw (lists)
@ 2016-12-15 16:08 ` Richard Earnshaw (lists)
2016-12-15 16:08 ` [PATCH 21/21] [arm] Permit 'auto' in -mfpu Richard Earnshaw (lists)
` (4 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:08 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 721 bytes --]
This converts the recently added implicit -mthumb support code to use
the new data structures. Since we have a very simple query and no
initialized copies of the sbitmaps, for now we simply scan the list of
features to look for the one of interest.
* arm-opts.h (struct arm_arch_core_flag): Add new field ISA.
Initialize it.
(arm_arch_core_flag): Delete flags field.
(arm_arch_core_flags): Don't initialize flags field.
* common/config/arm/arm-common.c (check_isa_bits_for): New function.
(arm_target_thumb_only): Use new isa bits arrays.
---
gcc/common/config/arm/arm-common.c | 23 +++++++++++++++++++----
gcc/config/arm/arm-opts.h | 1 +
2 files changed, 20 insertions(+), 4 deletions(-)
[-- Attachment #2: 0009-arm-Rework-arm-common-to-use-new-feature-bits.patch --]
[-- Type: text/x-patch, Size: 2216 bytes --]
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index 79e3f1f..dca3682 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -101,23 +101,37 @@ arm_rewrite_mcpu (int argc, const char **argv)
struct arm_arch_core_flag
{
const char *const name;
- const arm_feature_set flags;
+ const enum isa_feature isa_bits[isa_num_bits];
};
static const struct arm_arch_core_flag arm_arch_core_flags[] =
{
#undef ARM_CORE
#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
- {NAME, FLAGS},
+ {NAME, {ISA isa_nobit}},
#include "config/arm/arm-cores.def"
#undef ARM_CORE
#undef ARM_ARCH
#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS) \
- {NAME, FLAGS},
+ {NAME, {ISA isa_nobit}},
#include "config/arm/arm-arches.def"
#undef ARM_ARCH
};
+/* Scan over a raw feature array BITS checking for BIT being present.
+ This is slower than the normal bitmask checks, but we would spend longer
+ initializing that than doing the check this way. Returns true iff
+ BIT is found. */
+static bool
+check_isa_bits_for (const enum isa_feature* bits, enum isa_feature bit)
+{
+ while (*bits != isa_nobit)
+ if (*bits++ == bit)
+ return true;
+
+ return false;
+}
+
/* Called by the driver to check whether the target denoted by current
command line options is a Thumb-only target. ARGV is an array of
-march and -mcpu values (ie. it contains the rhs after the equal
@@ -132,7 +146,8 @@ arm_target_thumb_only (int argc, const char **argv)
{
for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++)
if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0)
- && !ARM_FSET_HAS_CPU1(arm_arch_core_flags[opt].flags, FL_NOTM))
+ && !check_isa_bits_for (arm_arch_core_flags[opt].isa_bits,
+ isa_bit_notm))
return "-mthumb";
return NULL;
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index a62ac46..52c69e9 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -26,6 +26,7 @@
#define ARM_OPTS_H
#include "arm-flags.h"
+#include "arm-isa.h"
/* The various ARM cores. */
enum processor_type
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 21/21] [arm] Permit 'auto' in -mfpu.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (15 preceding siblings ...)
2016-12-15 16:08 ` [PATCH 09/21] [arm] Rework arm-common to use new feature bits Richard Earnshaw (lists)
@ 2016-12-15 16:08 ` Richard Earnshaw (lists)
2016-12-15 16:08 ` [PATCH 10/21] [arm] Remove remaining references to arm feature sets Richard Earnshaw (lists)
` (3 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:08 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1640 bytes --]
Now we finally have the infrastructure in place we can now derive
details of the FPU from a CPU entry. This patch enables this for the
existing cores that already have an explicit FPU in their product names.
* arm-fpus.def: Add CNAME field to all FPU definitions.
* genopt.sh: Use explicit enumeration tags for FPU entries.
* arm-tables.opt: Regenerated.
* arm.opt (mfpu): Provide initial value.
* arm-opts.h (enum fpu_type): Build the enumeration from the list of
available FPUs. Add 'auto' entry on the end.
* arm.c (arm_configure_build_target): Only do explicit configuration
of the FPU features if the selected FPU is not 'auto'.
(arm_option_override): Adjust initialization of arm_fpu_index.
Emit an error if we have a hard float ABI request, but the processor
does not support floating-point.
(arm_option_print): Handle -mfpu=auto.
(arm_valid_target_attribute_rec): Don't permit fpu=auto in pragmas
or function attributes.
(arm_identify_fpu_from_isa): Handle effective soft-float when
the FPU is automatically detected.
* arm-cores.def (arm1136jf-s): Add feature ISA_FP_DBL.
(arm1176jzf-s): Likewise.
(mpcore): Likewise.
(arm1156t2f-s): Likewise.
---
gcc/config/arm/arm-cores.def | 8 +++----
gcc/config/arm/arm-fpus.def | 48 +++++++++++++++++++------------------
gcc/config/arm/arm-opts.h | 10 ++++++++
gcc/config/arm/arm-tables.opt | 46 +++++++++++++++++++-----------------
gcc/config/arm/arm.c | 55
++++++++++++++++++++++++++++++++++---------
gcc/config/arm/arm.opt | 2 +-
gcc/config/arm/genopt.sh | 15 +++++++-----
7 files changed, 117 insertions(+), 67 deletions(-)
[-- Attachment #2: 0021-arm-Permit-auto-in-mfpu.patch --]
[-- Type: text/x-patch, Size: 14804 bytes --]
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index a232d37..544579c 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -124,13 +124,13 @@ ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(I
/* V6 Architecture Processors */
ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j), 9e)
-ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz), 9e)
-ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k), 9e)
-ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e)
ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2), v6t2)
-ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), v6t2)
+ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), v6t2)
/* V6M Architecture Processors */
ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
index ae8197d..f07711c 100644
--- a/gcc/config/arm/arm-fpus.def
+++ b/gcc/config/arm/arm-fpus.def
@@ -19,31 +19,33 @@
/* Before using #include to read this file, define a macro:
- ARM_FPU(NAME, ISA)
+ ARM_FPU(NAME, CNAME, ISA)
- The arguments are the fields of struct arm_fpu_desc.
+ NAME is the publicly visible option name.
+ CNAME is a C-compatible variable name substring.
+ ISA is the list of feature bits that this FPU provides.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
-ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3))
-ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
-ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
-ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv))
-ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32))
-ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON))
-ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4))
-ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5))
-ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL))
-ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32))
-ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON))
-ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO))
+ARM_FPU("vfp", vfp, ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("vfpv2", vfpv2, ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("vfpv3", vfpv3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("vfpv3-fp16", vfpv3_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("vfpv3-d16", vfpv3_d16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("vfpv3-d16-fp16", vfpv3_d16_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("vfpv3xd", vfpv3xd, ISA_FEAT(ISA_VFPv3))
+ARM_FPU("vfpv3xd-fp16", vfpv3xd_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("neon", neon, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
+ARM_FPU("neon-vfpv3", neon_vfpv3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
+ARM_FPU("neon-fp16", neon_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("vfpv4", vfpv4, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("neon-vfpv4", neon_vfpv4, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON))
+ARM_FPU("vfpv4-d16", vfpv4_d16, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("fpv4-sp-d16", fpv4_sp_d16, ISA_FEAT(ISA_VFPv4))
+ARM_FPU("fpv5-sp-d16", fpv5_sp_d16, ISA_FEAT(ISA_FPv5))
+ARM_FPU("fpv5-d16", fpv5_d16, ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("fp-armv8", fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("neon-fp-armv8", neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON))
+ARM_FPU("crypto-neon-fp-armv8", crypto_neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO))
/* Compatibility aliases. */
-ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("vfp3", vfp3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index 3de110e..846abad 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -40,6 +40,16 @@ enum processor_type
TARGET_CPU_arm_none
};
+/* The various ARM FPUs. */
+enum fpu_type
+{
+#undef ARM_FPU
+#define ARM_FPU(NAME, CNAME, ISA) TARGET_FPU_##CNAME,
+#include "arm-fpus.def"
+ TARGET_FPU_auto
+#undef ARM_FPU
+};
+
/* Which __fp16 format to use.
The enumeration values correspond to the numbering for the
Tag_ABI_FP_16bit_format attribute.
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index faa00aa..574eadc 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -464,69 +464,71 @@ EnumValue
Enum(arm_arch) String(iwmmxt2) Value(34)
Enum
-Name(arm_fpu) Type(int)
+Name(arm_fpu) Type(enum fpu_type)
Known ARM FPUs (for use with the -mfpu= option):
EnumValue
-Enum(arm_fpu) String(vfp) Value(0)
+Enum(arm_fpu) String(vfp) Value(TARGET_FPU_vfp)
EnumValue
-Enum(arm_fpu) String(vfpv2) Value(1)
+Enum(arm_fpu) String(vfpv2) Value(TARGET_FPU_vfpv2)
EnumValue
-Enum(arm_fpu) String(vfpv3) Value(2)
+Enum(arm_fpu) String(vfpv3) Value(TARGET_FPU_vfpv3)
EnumValue
-Enum(arm_fpu) String(vfpv3-fp16) Value(3)
+Enum(arm_fpu) String(vfpv3-fp16) Value(TARGET_FPU_vfpv3_fp16)
EnumValue
-Enum(arm_fpu) String(vfpv3-d16) Value(4)
+Enum(arm_fpu) String(vfpv3-d16) Value(TARGET_FPU_vfpv3_d16)
EnumValue
-Enum(arm_fpu) String(vfpv3-d16-fp16) Value(5)
+Enum(arm_fpu) String(vfpv3-d16-fp16) Value(TARGET_FPU_vfpv3_d16_fp16)
EnumValue
-Enum(arm_fpu) String(vfpv3xd) Value(6)
+Enum(arm_fpu) String(vfpv3xd) Value(TARGET_FPU_vfpv3xd)
EnumValue
-Enum(arm_fpu) String(vfpv3xd-fp16) Value(7)
+Enum(arm_fpu) String(vfpv3xd-fp16) Value(TARGET_FPU_vfpv3xd_fp16)
EnumValue
-Enum(arm_fpu) String(neon) Value(8)
+Enum(arm_fpu) String(neon) Value(TARGET_FPU_neon)
EnumValue
-Enum(arm_fpu) String(neon-vfpv3) Value(9)
+Enum(arm_fpu) String(neon-vfpv3) Value(TARGET_FPU_neon_vfpv3)
EnumValue
-Enum(arm_fpu) String(neon-fp16) Value(10)
+Enum(arm_fpu) String(neon-fp16) Value(TARGET_FPU_neon_fp16)
EnumValue
-Enum(arm_fpu) String(vfpv4) Value(11)
+Enum(arm_fpu) String(vfpv4) Value(TARGET_FPU_vfpv4)
EnumValue
-Enum(arm_fpu) String(neon-vfpv4) Value(12)
+Enum(arm_fpu) String(neon-vfpv4) Value(TARGET_FPU_neon_vfpv4)
EnumValue
-Enum(arm_fpu) String(vfpv4-d16) Value(13)
+Enum(arm_fpu) String(vfpv4-d16) Value(TARGET_FPU_vfpv4_d16)
EnumValue
-Enum(arm_fpu) String(fpv4-sp-d16) Value(14)
+Enum(arm_fpu) String(fpv4-sp-d16) Value(TARGET_FPU_fpv4_sp_d16)
EnumValue
-Enum(arm_fpu) String(fpv5-sp-d16) Value(15)
+Enum(arm_fpu) String(fpv5-sp-d16) Value(TARGET_FPU_fpv5_sp_d16)
EnumValue
-Enum(arm_fpu) String(fpv5-d16) Value(16)
+Enum(arm_fpu) String(fpv5-d16) Value(TARGET_FPU_fpv5_d16)
EnumValue
-Enum(arm_fpu) String(fp-armv8) Value(17)
+Enum(arm_fpu) String(fp-armv8) Value(TARGET_FPU_fp_armv8)
EnumValue
-Enum(arm_fpu) String(neon-fp-armv8) Value(18)
+Enum(arm_fpu) String(neon-fp-armv8) Value(TARGET_FPU_neon_fp_armv8)
EnumValue
-Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(19)
+Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(TARGET_FPU_crypto_neon_fp_armv8)
EnumValue
-Enum(arm_fpu) String(vfp3) Value(20)
+Enum(arm_fpu) String(vfp3) Value(TARGET_FPU_vfp3)
+EnumValue
+Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 522989d..f068796 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2328,7 +2328,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
const struct arm_fpu_desc all_fpus[] =
{
-#define ARM_FPU(NAME, ISA) \
+#undef ARM_FPU
+#define ARM_FPU(NAME, CNAME, ISA) \
{ NAME, {ISA isa_nobit} },
#include "arm-fpus.def"
#undef ARM_FPU
@@ -3255,12 +3256,19 @@ arm_configure_build_target (struct arm_build_target *target,
gcc_assert (arm_selected_cpu);
- arm_selected_fpu = &all_fpus[opts->x_arm_fpu_index];
- auto_sbitmap fpu_bits (isa_num_bits);
+ if (opts->x_arm_fpu_index != TARGET_FPU_auto)
+ {
+ arm_selected_fpu = &all_fpus[opts->x_arm_fpu_index];
+ auto_sbitmap fpu_bits (isa_num_bits);
- arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits);
- bitmap_and_compl (target->isa, target->isa, isa_all_fpubits);
- bitmap_ior (target->isa, target->isa, fpu_bits);
+ arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits);
+ bitmap_and_compl (target->isa, target->isa, isa_all_fpubits);
+ bitmap_ior (target->isa, target->isa, fpu_bits);
+ }
+ else if (target->core_name == NULL)
+ /* To support this we need to be able to parse FPU feature options
+ from the architecture string. */
+ sorry ("-mfpu=auto not currently supported without an explicit CPU.");
/* The selected cpu may be an architecture, so lookup tuning by core ID. */
if (!arm_selected_tune)
@@ -3295,6 +3303,7 @@ arm_option_override (void)
{
const char *target_fpu_name;
bool ok;
+ int fpu_index;
#ifdef FPUTYPE_DEFAULT
target_fpu_name = FPUTYPE_DEFAULT;
@@ -3302,9 +3311,10 @@ arm_option_override (void)
target_fpu_name = "vfp";
#endif
- ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index,
+ ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &fpu_index,
CL_TARGET);
gcc_assert (ok);
+ arm_fpu_index = (enum fpu_type) fpu_index;
}
/* Create the default target_options structure. We need this early
@@ -3448,7 +3458,11 @@ arm_option_override (void)
arm_pcs_default = ARM_PCS_AAPCS_IWMMXT;
else if (arm_float_abi == ARM_FLOAT_ABI_HARD
&& TARGET_HARD_FLOAT)
- arm_pcs_default = ARM_PCS_AAPCS_VFP;
+ {
+ arm_pcs_default = ARM_PCS_AAPCS_VFP;
+ if (!bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv2))
+ error ("-mfloat-abi=hard: selected processor lacks an FPU");
+ }
else
arm_pcs_default = ARM_PCS_AAPCS;
}
@@ -30210,14 +30224,17 @@ static void
arm_option_print (FILE *file, int indent, struct cl_target_option *ptr)
{
int flags = ptr->x_target_flags;
- const struct arm_fpu_desc *fpu_desc = &all_fpus[ptr->x_arm_fpu_index];
+ const char *fpu_name;
+
+ fpu_name = (ptr->x_arm_fpu_index == TARGET_FPU_auto
+ ? "auto" : all_fpus[ptr->x_arm_fpu_index].name);
fprintf (file, "%*sselected arch %s\n", indent, "",
TARGET_THUMB2_P (flags) ? "thumb2" :
TARGET_THUMB_P (flags) ? "thumb1" :
"arm");
- fprintf (file, "%*sselected fpu %s\n", indent, "", fpu_desc->name);
+ fprintf (file, "%*sselected fpu %s\n", indent, "", fpu_name);
}
/* Hook to determine if one function can safely inline another. */
@@ -30319,12 +30336,22 @@ arm_valid_target_attribute_rec (tree args, struct gcc_options *opts)
else if (!strncmp (q, "fpu=", 4))
{
+ int fpu_index;
if (! opt_enum_arg_to_value (OPT_mfpu_, q+4,
- &opts->x_arm_fpu_index, CL_TARGET))
+ &fpu_index, CL_TARGET))
{
error ("invalid fpu for attribute(target(\"%s\"))", q);
return false;
}
+ if (fpu_index == TARGET_FPU_auto)
+ {
+ /* This doesn't really make sense until we support
+ general dynamic selection of the architecture and all
+ sub-features. */
+ sorry ("auto fpu selection not currently permitted here");
+ return false;
+ }
+ opts->x_arm_fpu_index = (enum fpu_type) fpu_index;
}
else
{
@@ -30465,6 +30492,12 @@ arm_identify_fpu_from_isa (sbitmap isa)
auto_sbitmap cand_fpubits (isa_num_bits);
bitmap_and (fpubits, isa, isa_all_fpubits);
+
+ /* If there are no ISA feature bits relating to the FPU, we must be
+ doing soft-float. */
+ if (bitmap_empty_p (fpubits))
+ return "softvfp";
+
for (unsigned int i = 0; i < ARRAY_SIZE (all_fpus); i++)
{
arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits);
diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
index 934144d..3c877b1 100644
--- a/gcc/config/arm/arm.opt
+++ b/gcc/config/arm/arm.opt
@@ -144,7 +144,7 @@ EnumValue
Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE)
mfpu=
-Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Save
+Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Init(TARGET_FPU_auto) Save
Specify the name of the target floating point hardware/format.
mhard-float
diff --git a/gcc/config/arm/genopt.sh b/gcc/config/arm/genopt.sh
index 82e5436..3b75711 100755
--- a/gcc/config/arm/genopt.sh
+++ b/gcc/config/arm/genopt.sh
@@ -77,19 +77,22 @@ awk -F'[(, ]+' 'BEGIN {
cat <<EOF
Enum
-Name(arm_fpu) Type(int)
+Name(arm_fpu) Type(enum fpu_type)
Known ARM FPUs (for use with the -mfpu= option):
EOF
-awk -F'[(, ]+' 'BEGIN {
- value = 0
-}
+awk -F'[(, ]+' '
/^ARM_FPU/ {
name = $2
+ enum = $3
gsub("\"", "", name)
print "EnumValue"
- print "Enum(arm_fpu) String(" name ") Value(" value ")"
+ print "Enum(arm_fpu) String(" name ") Value(TARGET_FPU_" enum ")"
print ""
- value++
+}
+END {
+ print "EnumValue"
+ print "Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto)"
}' $1/arm-fpus.def
+
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 10/21] [arm] Remove remaining references to arm feature sets.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (16 preceding siblings ...)
2016-12-15 16:08 ` [PATCH 21/21] [arm] Permit 'auto' in -mfpu Richard Earnshaw (lists)
@ 2016-12-15 16:08 ` Richard Earnshaw (lists)
2016-12-15 16:08 ` [PATCH 13/21] [arm] Remove FPU rev field Richard Earnshaw (lists)
` (2 subsequent siblings)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:08 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 947 bytes --]
Nothing uses the old feature sets now, so we can delete them entirely.
* arm-cores.def: Remove FLAGS field from all core definitions.
* arm-arches.def: Likewise.
* arm-opts.h (enum processor_type): Remove FLAGS parameter from
ARM_CORES macro.
(arm_arch_core_flags): Likewise, plus ARM_ARCH macro.
* arm-protos.h (FL_*): Delete.
(arm_feature_set): Delete.
(ARM_FSET_*): Delete.
* arm.c (struct processors): Delete flags field.
(all_cores): Delete FLAGS parameter from macro, don't initialize flags.
(all architectures): Likewise.
---
gcc/common/config/arm/arm-common.c | 4 +-
gcc/config/arm/arm-arches.def | 75 ++++++-------
gcc/config/arm/arm-cores.def | 224
++++++++++++++++++-------------------
gcc/config/arm/arm-flags.h | 185 ------------------------------
gcc/config/arm/arm-opts.h | 2 +-
gcc/config/arm/arm.c | 14 +--
6 files changed, 157 insertions(+), 347 deletions(-)
[-- Attachment #2: 0010-arm-Remove-remaining-references-to-arm-feature-sets.patch --]
[-- Type: text/x-patch, Size: 50118 bytes --]
diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c
index dca3682..611675b 100644
--- a/gcc/common/config/arm/arm-common.c
+++ b/gcc/common/config/arm/arm-common.c
@@ -107,12 +107,12 @@ struct arm_arch_core_flag
static const struct arm_arch_core_flag arm_arch_core_flags[] =
{
#undef ARM_CORE
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
{NAME, {ISA isa_nobit}},
#include "config/arm/arm-cores.def"
#undef ARM_CORE
#undef ARM_ARCH
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS) \
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA) \
{NAME, {ISA isa_nobit}},
#include "config/arm/arm-arches.def"
#undef ARM_ARCH
diff --git a/gcc/config/arm/arm-arches.def b/gcc/config/arm/arm-arches.def
index 02ece42..ed6b0b6 100644
--- a/gcc/config/arm/arm-arches.def
+++ b/gcc/config/arm/arm-arches.def
@@ -19,50 +19,49 @@
/* Before using #include to read this file, define a macro:
- ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS)
+ ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA)
The NAME is the name of the architecture, represented as a string
constant. The CORE is the identifier for a core representative of
this architecture. ARCH is the architecture revision. ISA is the
detailed architectural capabilities of the core (see arm-isa.h).
- FLAGS is the set of feature flags implied by the architecture.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2))
-ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3))
-ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M))
-ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4))
-/* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
+ARM_ARCH("armv2", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv2a", arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv3", arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv3m", arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26))
+ARM_ARCH("armv4", arm7tdmi, TF_CO_PROC, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26))
+/* Strictly, isa_bit_mode26 is a permitted option for v4t, but there are no
implementations that support it, so we will leave it out for now. */
-ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T))
-ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ISA_FEAT(ISA_ARMv5), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5))
-ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T))
-ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ISA_FEAT(ISA_ARMv5e), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5E))
-ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE))
-ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ISA_FEAT(ISA_ARMv6), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6))
-ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J))
-ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K))
-ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ISA_FEAT(ISA_ARMv6z), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6Z))
-ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ))
-ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2))
-ARM_ARCH("armv6-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M))
-ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ISA_FEAT(ISA_ARMv7), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7))
-ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A))
-ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7VE))
-ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R))
-ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ISA_FEAT(ISA_ARMv7m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M))
-ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM))
-ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A))
-ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A))
-ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_1a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_1A))
-ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A))
-ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16), ARM_FSET_MAKE (FL_CRC32 | FL_FOR_ARCH8A, FL2_FOR_ARCH8_2A | FL2_FP16INST))
-ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE (FL_FOR_ARCH8M_BASE, FL2_CMSE))
-ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main), ARM_FSET_MAKE (FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN, FL2_CMSE))
-ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT))
-ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT | FL_IWMMXT2))
+ARM_ARCH("armv4t", arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t))
+ARM_ARCH("armv5", arm10tdmi, TF_CO_PROC, 5, ISA_FEAT(ISA_ARMv5))
+ARM_ARCH("armv5t", arm10tdmi, TF_CO_PROC, 5T, ISA_FEAT(ISA_ARMv5t))
+ARM_ARCH("armv5e", arm1026ejs, TF_CO_PROC, 5E, ISA_FEAT(ISA_ARMv5e))
+ARM_ARCH("armv5te", arm1026ejs, TF_CO_PROC, 5TE, ISA_FEAT(ISA_ARMv5te))
+ARM_ARCH("armv6", arm1136js, TF_CO_PROC, 6, ISA_FEAT(ISA_ARMv6))
+ARM_ARCH("armv6j", arm1136js, TF_CO_PROC, 6J, ISA_FEAT(ISA_ARMv6j))
+ARM_ARCH("armv6k", mpcore, TF_CO_PROC, 6K, ISA_FEAT(ISA_ARMv6k))
+ARM_ARCH("armv6z", arm1176jzs, TF_CO_PROC, 6Z, ISA_FEAT(ISA_ARMv6z))
+ARM_ARCH("armv6kz", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz))
+ARM_ARCH("armv6zk", arm1176jzs, TF_CO_PROC, 6KZ, ISA_FEAT(ISA_ARMv6kz))
+ARM_ARCH("armv6t2", arm1156t2s, TF_CO_PROC, 6T2, ISA_FEAT(ISA_ARMv6t2))
+ARM_ARCH("armv6-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m))
+ARM_ARCH("armv6s-m", cortexm1, 0, 6M, ISA_FEAT(ISA_ARMv6m))
+ARM_ARCH("armv7", cortexa8, TF_CO_PROC, 7, ISA_FEAT(ISA_ARMv7))
+ARM_ARCH("armv7-a", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7a))
+ARM_ARCH("armv7ve", cortexa8, TF_CO_PROC, 7A, ISA_FEAT(ISA_ARMv7ve))
+ARM_ARCH("armv7-r", cortexr4, TF_CO_PROC, 7R, ISA_FEAT(ISA_ARMv7r))
+ARM_ARCH("armv7-m", cortexm3, TF_CO_PROC, 7M, ISA_FEAT(ISA_ARMv7m))
+ARM_ARCH("armv7e-m", cortexm4, TF_CO_PROC, 7EM, ISA_FEAT(ISA_ARMv7em))
+ARM_ARCH("armv8-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a))
+ARM_ARCH("armv8-a+crc",cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32))
+ARM_ARCH("armv8.1-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_1a))
+ARM_ARCH ("armv8.2-a", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a))
+ARM_ARCH ("armv8.2-a+fp16", cortexa53, TF_CO_PROC, 8A, ISA_FEAT(ISA_ARMv8_2a) ISA_FEAT(isa_bit_fp16))
+ARM_ARCH("armv8-m.base", cortexm23, 0, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base))
+ARM_ARCH("armv8-m.main", cortexm7, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main))
+ARM_ARCH("armv8-m.main+dsp", cortexm33, TF_CO_PROC, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em))
+ARM_ARCH("iwmmxt", iwmmxt, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt))
+ARM_ARCH("iwmmxt2", iwmmxt2, (TF_LDSCHED | TF_STRONG | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2))
diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def
index 7f64a1f..a232d37 100644
--- a/gcc/config/arm/arm-cores.def
+++ b/gcc/config/arm/arm-cores.def
@@ -25,7 +25,7 @@
/* Before using #include to read this file, define a macro:
- ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS)
+ ARM_CORE(CORE_NAME, INTERNAL_IDENT, TUNE_IDENT, TUNE_FLAGS, ARCH, ISA, COSTS)
The CORE_NAME is the name of the core, represented as a string constant.
The INTERNAL_IDENT is the name of the core represented as an identifier.
@@ -35,8 +35,6 @@
TUNE_FLAGS is a set of flag bits that are used to affect tuning.
ARCH is the architecture revision implemented by the chip.
ISA is the detailed architectural capabilities of the core (see arm-isa.h).
- FLAGS is the set of feature flags of that core.
- This need not include flags implied by the architecture.
COSTS is the name of the rtx_costs routine to use.
If you update this table, you must update the "tune" attribute in
@@ -45,146 +43,146 @@
Some tools assume no whitespace up to the first "," in each entry. */
/* V2/V2A Architecture Processors */
-ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
-ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH2), slowmul)
+ARM_CORE("arm2", arm2, arm2, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm250", arm250, arm250, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm3", arm3, arm3, (TF_CO_PROC | TF_NO_MODE32), 2, ISA_FEAT(ISA_ARMv2) ISA_FEAT(isa_bit_mode26), slowmul)
/* V3 Architecture Processors */
-ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
-ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm6", arm6, arm6, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm60", arm60, arm60, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm600", arm600, arm600, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm610", arm610, arm610, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm620", arm620, arm620, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7", arm7, arm7, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7d", arm7d, arm7d, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7di", arm7di, arm7di, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm70", arm70, arm70, TF_CO_PROC, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm700", arm700, arm700, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm700i", arm700i, arm700i, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm710", arm710, arm710, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm720", arm720, arm720, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm710c", arm710c, arm710c, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7100", arm7100, arm7100, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
+ARM_CORE("arm7500", arm7500, arm7500, TF_WBUF, 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
/* Doesn't have an external co-proc, but does have embedded fpa (fpa no-longer supported). */
-ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3), slowmul)
+ARM_CORE("arm7500fe", arm7500fe, arm7500fe, (TF_CO_PROC | TF_WBUF), 3, ISA_FEAT(ISA_ARMv3) ISA_FEAT(isa_bit_mode26), slowmul)
/* V3M Architecture Processors */
/* arm7m doesn't exist on its own, but only with D, ("and", and I), but
those don't alter the code, so arm7m is sometimes used. */
-ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
-ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH3M), fastmul)
+ARM_CORE("arm7m", arm7m, arm7m, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("arm7dm", arm7dm, arm7dm, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("arm7dmi", arm7dmi, arm7dmi, TF_CO_PROC, 3M, ISA_FEAT(ISA_ARMv3m) ISA_FEAT(isa_bit_mode26), fastmul)
/* V4 Architecture Processors */
-ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), fastmul)
-ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), ARM_FSET_MAKE_CPU1 (FL_MODE26 | FL_FOR_ARCH4), strongarm)
-ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
-ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4), fastmul)
+ARM_CORE("arm8", arm8, arm8, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("arm810", arm810, arm810, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), fastmul)
+ARM_CORE("strongarm", strongarm, strongarm, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("strongarm110", strongarm110, strongarm110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("strongarm1100", strongarm1100, strongarm1100, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("strongarm1110", strongarm1110, strongarm1110, (TF_LDSCHED | TF_STRONG), 4, ISA_FEAT(ISA_ARMv4) ISA_FEAT(isa_bit_mode26), strongarm)
+ARM_CORE("fa526", fa526, fa526, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), fastmul)
+ARM_CORE("fa626", fa626, fa626, TF_LDSCHED, 4, ISA_FEAT(ISA_ARMv4), fastmul)
/* V4T Architecture Processors */
-ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
-ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH4T), fastmul)
+ARM_CORE("arm7tdmi", arm7tdmi, arm7tdmi, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm7tdmi-s", arm7tdmis, arm7tdmis, TF_CO_PROC, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm710t", arm710t, arm710t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm720t", arm720t, arm720t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm740t", arm740t, arm740t, TF_WBUF, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm9", arm9, arm9, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm9tdmi", arm9tdmi, arm9tdmi, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm920", arm920, arm920, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm920t", arm920t, arm920t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm922t", arm922t, arm922t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("arm940t", arm940t, arm940t, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
+ARM_CORE("ep9312", ep9312, ep9312, TF_LDSCHED, 4T, ISA_FEAT(ISA_ARMv4t), fastmul)
/* V5T Architecture Processors */
-ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
-ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5T), fastmul)
+ARM_CORE("arm10tdmi", arm10tdmi, arm10tdmi, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), fastmul)
+ARM_CORE("arm1020t", arm1020t, arm1020t, TF_LDSCHED, 5T, ISA_FEAT(ISA_ARMv5t), fastmul)
/* V5TE Architecture Processors */
-ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fastmul)
-ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), ARM_FSET_MAKE_CPU1 (FL_XSCALE | FL_IWMMXT | FL_IWMMXT2 | FL_FOR_ARCH5TE), xscale)
-ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), 9e)
-ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TE), fa726te)
+ARM_CORE("arm9e", arm9e, arm9e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm946e-s", arm946es, arm946es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm966e-s", arm966es, arm966es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm968e-s", arm968es, arm968es, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("arm10e", arm10e, arm10e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fastmul)
+ARM_CORE("arm1020e", arm1020e, arm1020e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fastmul)
+ARM_CORE("arm1022e", arm1022e, arm1022e, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fastmul)
+ARM_CORE("xscale", xscale, xscale, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale), xscale)
+ARM_CORE("iwmmxt", iwmmxt, iwmmxt, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt), xscale)
+ARM_CORE("iwmmxt2", iwmmxt2, iwmmxt2, (TF_LDSCHED | TF_XSCALE), 5TE, ISA_FEAT(ISA_ARMv5te) ISA_FEAT(isa_bit_xscale) ISA_FEAT(isa_bit_iwmmxt) ISA_FEAT(isa_bit_iwmmxt2), xscale)
+ARM_CORE("fa606te", fa606te, fa606te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("fa626te", fa626te, fa626te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("fmp626", fmp626, fmp626, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), 9e)
+ARM_CORE("fa726te", fa726te, fa726te, TF_LDSCHED, 5TE, ISA_FEAT(ISA_ARMv5te), fa726te)
/* V5TEJ Architecture Processors */
-ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
-ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH5TEJ), 9e)
+ARM_CORE("arm926ej-s", arm926ejs, arm926ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), 9e)
+ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(ISA_ARMv5tej), 9e)
/* V6 Architecture Processors */
-ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6J), 9e)
-ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6KZ), 9e)
-ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6K), 9e)
-ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6K), 9e)
-ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6T2), v6t2)
-ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), ARM_FSET_MAKE_CPU1 (FL_VFPV2 | FL_FOR_ARCH6T2), v6t2)
+ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j), 9e)
+ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz), 9e)
+ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k), 9e)
+ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), 9e)
+ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2), v6t2)
+ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), v6t2)
/* V6M Architecture Processors */
-ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0", cortexm0, cortexm0, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0plus", cortexm0plus, cortexm0plus, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m)
/* V6M Architecture Processors for small-multiply implementations. */
-ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
-ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH6M), v6m)
+ARM_CORE("cortex-m1.small-multiply", cortexm1smallmultiply, cortexm1, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0.small-multiply", cortexm0smallmultiply, cortexm0, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), v6m)
+ARM_CORE("cortex-m0plus.small-multiply",cortexm0plussmallmultiply, cortexm0plus, (TF_LDSCHED | TF_SMALLMUL), 6M, ISA_FEAT(ISA_ARMv6m), v6m)
/* V7 Architecture Processors */
-ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex)
-ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a5)
-ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a7)
-ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a8)
-ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), cortex_a9)
-ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
-ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), ARM_FSET_MAKE_CPU1 (FL_ARM_DIV | FL_FOR_ARCH7R), cortex)
-ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), ARM_FSET_MAKE_CPU1 (FL_NO_VOLATILE_CE | FL_FOR_ARCH7EM), cortex_m7)
-ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7EM), v7m)
-ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7M), v7m)
-ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH7A), marvell_pj4)
+ARM_CORE("generic-armv7-a", genericv7a, genericv7a, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex)
+ARM_CORE("cortex-a5", cortexa5, cortexa5, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex_a5)
+ARM_CORE("cortex-a7", cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a7)
+ARM_CORE("cortex-a8", cortexa8, cortexa8, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex_a8)
+ARM_CORE("cortex-a9", cortexa9, cortexa9, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), cortex_a9)
+ARM_CORE("cortex-a12", cortexa12, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a) ISA_FEAT(isa_bit_adiv) ISA_FEAT(isa_bit_tdiv), cortex_a12)
+ARM_CORE("cortex-a15", cortexa15, cortexa15, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a15)
+ARM_CORE("cortex-a17", cortexa17, cortexa17, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a12)
+ARM_CORE("cortex-r4", cortexr4, cortexr4, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), cortex)
+ARM_CORE("cortex-r4f", cortexr4f, cortexr4f, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r), cortex)
+ARM_CORE("cortex-r5", cortexr5, cortexr5, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
+ARM_CORE("cortex-r7", cortexr7, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
+ARM_CORE("cortex-r8", cortexr8, cortexr7, TF_LDSCHED, 7R, ISA_FEAT(ISA_ARMv7r) ISA_FEAT(isa_bit_adiv), cortex)
+ARM_CORE("cortex-m7", cortexm7, cortexm7, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em) ISA_FEAT(isa_quirk_no_volatile_ce), cortex_m7)
+ARM_CORE("cortex-m4", cortexm4, cortexm4, TF_LDSCHED, 7EM, ISA_FEAT(ISA_ARMv7em), v7m)
+ARM_CORE("cortex-m3", cortexm3, cortexm3, TF_LDSCHED, 7M, ISA_FEAT(ISA_ARMv7m) ISA_FEAT(isa_quirk_cm3_ldrd), v7m)
+ARM_CORE("marvell-pj4", marvell_pj4, marvell_pj4, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7a), marvell_pj4)
/* V7 big.LITTLE implementations */
-ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a15)
-ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), ARM_FSET_MAKE_CPU1 (FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12)
+ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a15)
+ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, TF_LDSCHED, 7A, ISA_FEAT(ISA_ARMv7ve), cortex_a12)
/* V8 A-profile Architecture Processors */
-ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a35)
-ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a53)
-ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), exynosm1)
-ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), qdf24xx)
-ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8A), xgene1)
+ARM_CORE("cortex-a32", cortexa32, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
+ARM_CORE("cortex-a35", cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a35)
+ARM_CORE("cortex-a53", cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a53)
+ARM_CORE("cortex-a57", cortexa57, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a72", cortexa72, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a73", cortexa73, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
+ARM_CORE("exynos-m1", exynosm1, exynosm1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), exynosm1)
+ARM_CORE("falkor", falkor, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
+ARM_CORE("qdf24xx", qdf24xx, cortexa57, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), qdf24xx)
+ARM_CORE("xgene1", xgene1, xgene1, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a), xgene1)
/* V8 A-profile big.LITTLE implementations */
-ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a57)
-ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
-ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), ARM_FSET_MAKE_CPU1 (FL_CRC32 | FL_FOR_ARCH8A), cortex_a73)
+ARM_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a57)
+ARM_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
+ARM_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, TF_LDSCHED, 8A, ISA_FEAT(ISA_ARMv8a) ISA_FEAT(isa_bit_crc32), cortex_a73)
/* V8 M-profile implementations. */
-ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base), ARM_FSET_MAKE_CPU1 (FL_FOR_ARCH8M_BASE), v6m)
-ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), ARM_FSET_MAKE_CPU1 (FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m)
+ARM_CORE("cortex-m23", cortexm23, cortexm23, TF_LDSCHED, 8M_BASE, ISA_FEAT(ISA_ARMv8m_base), v6m)
+ARM_CORE("cortex-m33", cortexm33, cortexm33, TF_LDSCHED, 8M_MAIN, ISA_FEAT(ISA_ARMv8m_main) ISA_FEAT(isa_bit_ARMv7em), v7m)
diff --git a/gcc/config/arm/arm-flags.h b/gcc/config/arm/arm-flags.h
index 6482c64..a0d99a8 100644
--- a/gcc/config/arm/arm-flags.h
+++ b/gcc/config/arm/arm-flags.h
@@ -32,189 +32,4 @@
#define TF_XSCALE (1U << 5)
#define TF_NO_MODE32 (1U << 6)
-/* Flags used to identify the presence of processor capabilities. */
-
-/* Bit values used to identify processor capabilities. */
-#define FL_NONE (0U) /* No flags. */
-#define FL_ANY (0xffffffffU) /* All flags. */
-#define FL_CO_PROC (1U << 0) /* Has external co-processor bus. */
-#define FL_ARCH3M (1U << 1) /* Extended multiply. */
-#define FL_MODE26 (1U << 2) /* 26-bit mode support. */
-#define FL_MODE32 (1U << 3) /* 32-bit mode support. */
-#define FL_ARCH4 (1U << 4) /* Architecture rel 4. */
-#define FL_ARCH5 (1U << 5) /* Architecture rel 5. */
-#define FL_THUMB (1U << 6) /* Thumb aware. */
-/* Spare (1U << 7) */
-/* Spare (1U << 8) */
-#define FL_ARCH5E (1U << 9) /* DSP extensions to v5. */
-#define FL_XSCALE (1U << 10) /* XScale. */
-/* Spare (1U << 11) */
-#define FL_ARCH6 (1U << 12) /* Architecture rel 6. Adds
- media instructions. */
-#define FL_VFPV2 (1U << 13) /* Vector Floating Point V2. */
-/* Spare (1U << 14) */
-#define FL_ARCH6K (1U << 15) /* Architecture rel 6 K extensions. */
-#define FL_THUMB2 (1U << 16) /* Thumb-2. */
-#define FL_NOTM (1U << 17) /* Instructions not present in the 'M'
- profile. */
-#define FL_THUMB_DIV (1U << 18) /* Hardware divide (Thumb mode). */
-#define FL_VFPV3 (1U << 19) /* Vector Floating Point V3. */
-#define FL_NEON (1U << 20) /* Neon instructions. */
-#define FL_ARCH7EM (1U << 21) /* Instructions present in the ARMv7E-M
- architecture. */
-#define FL_ARCH7 (1U << 22) /* Architecture 7. */
-#define FL_ARM_DIV (1U << 23) /* Hardware divide (ARM mode). */
-#define FL_ARCH8 (1U << 24) /* Architecture 8. */
-#define FL_CRC32 (1U << 25) /* ARMv8 CRC32 instructions. */
-/* Spare (1U << 26) */
-#define FL_NO_VOLATILE_CE (1U << 27) /* No volatile memory in IT block. */
-
-#define FL_IWMMXT (1U << 29) /* XScale v2 or "Intel Wireless MMX
- technology". */
-#define FL_IWMMXT2 (1U << 30) /* "Intel Wireless MMX2
- technology". */
-#define FL_ARCH6KZ (1U << 31) /* ARMv6KZ architecture. */
-
-#define FL2_ARCH8_1 (1U << 0) /* Architecture 8.1. */
-#define FL2_ARCH8_2 (1U << 1) /* Architecture 8.2. */
-#define FL2_FP16INST (1U << 2) /* FP16 Instructions for ARMv8.2 and
- later. */
-#define FL2_CMSE (1U << 3) /* ARMv8-M Security Extensions. */
-
-/* Flags that only effect tuning, not available instructions. */
-#define FL_TUNE (FL_VFPV2)
-
-#define FL_FOR_ARCH2 FL_NOTM
-#define FL_FOR_ARCH3 (FL_FOR_ARCH2 | FL_MODE32)
-#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M)
-#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4)
-#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB)
-#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5)
-#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB)
-#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E)
-#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB)
-#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE
-#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6)
-#define FL_FOR_ARCH6J FL_FOR_ARCH6
-#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K)
-#define FL_FOR_ARCH6Z FL_FOR_ARCH6
-#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K
-#define FL_FOR_ARCH6KZ (FL_FOR_ARCH6K | FL_ARCH6KZ)
-#define FL_FOR_ARCH6T2 (FL_FOR_ARCH6 | FL_THUMB2)
-#define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM)
-#define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7)
-#define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K)
-#define FL_FOR_ARCH7VE (FL_FOR_ARCH7A | FL_THUMB_DIV | FL_ARM_DIV)
-#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV)
-#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV)
-#define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM)
-#define FL_FOR_ARCH8A (FL_FOR_ARCH7VE | FL_ARCH8)
-#define FL2_FOR_ARCH8_1A FL2_ARCH8_1
-#define FL2_FOR_ARCH8_2A (FL2_FOR_ARCH8_1A | FL2_ARCH8_2)
-#define FL_FOR_ARCH8M_BASE (FL_FOR_ARCH6M | FL_ARCH8 | FL_THUMB_DIV)
-#define FL_FOR_ARCH8M_MAIN (FL_FOR_ARCH7M | FL_ARCH8)
-
-/* There are too many feature bits to fit in a single word so the set of cpu and
- fpu capabilities is a structure. A feature set is created and manipulated
- with the ARM_FSET macros. */
-
-typedef struct
-{
- unsigned cpu[2];
-} arm_feature_set;
-
-
-/* Initialize a feature set. */
-
-#define ARM_FSET_MAKE(CPU1,CPU2) { { (CPU1), (CPU2) } }
-
-#define ARM_FSET_MAKE_CPU1(CPU1) ARM_FSET_MAKE ((CPU1), (FL_NONE))
-#define ARM_FSET_MAKE_CPU2(CPU2) ARM_FSET_MAKE ((FL_NONE), (CPU2))
-
-/* Accessors. */
-
-#define ARM_FSET_CPU1(S) ((S).cpu[0])
-#define ARM_FSET_CPU2(S) ((S).cpu[1])
-
-/* Useful combinations. */
-
-#define ARM_FSET_EMPTY ARM_FSET_MAKE (FL_NONE, FL_NONE)
-#define ARM_FSET_ANY ARM_FSET_MAKE (FL_ANY, FL_ANY)
-
-/* Tests for a specific CPU feature. */
-
-#define ARM_FSET_HAS_CPU1(A, F) \
- (((A).cpu[0] & ((unsigned long)(F))) == ((unsigned long)(F)))
-#define ARM_FSET_HAS_CPU2(A, F) \
- (((A).cpu[1] & ((unsigned long)(F))) == ((unsigned long)(F)))
-#define ARM_FSET_HAS_CPU(A, F1, F2) \
- (ARM_FSET_HAS_CPU1 ((A), (F1)) && ARM_FSET_HAS_CPU2 ((A), (F2)))
-
-/* Add a feature to a feature set. */
-
-#define ARM_FSET_ADD_CPU1(DST, F) \
- do { \
- (DST).cpu[0] |= (F); \
- } while (0)
-
-#define ARM_FSET_ADD_CPU2(DST, F) \
- do { \
- (DST).cpu[1] |= (F); \
- } while (0)
-
-/* Remove a feature from a feature set. */
-
-#define ARM_FSET_DEL_CPU1(DST, F) \
- do { \
- (DST).cpu[0] &= ~(F); \
- } while (0)
-
-#define ARM_FSET_DEL_CPU2(DST, F) \
- do { \
- (DST).cpu[1] &= ~(F); \
- } while (0)
-
-/* Union of feature sets. */
-
-#define ARM_FSET_UNION(DST,F1,F2) \
- do { \
- (DST).cpu[0] = (F1).cpu[0] | (F2).cpu[0]; \
- (DST).cpu[1] = (F1).cpu[1] | (F2).cpu[1]; \
- } while (0)
-
-/* Intersection of feature sets. */
-
-#define ARM_FSET_INTER(DST,F1,F2) \
- do { \
- (DST).cpu[0] = (F1).cpu[0] & (F2).cpu[0]; \
- (DST).cpu[1] = (F1).cpu[1] & (F2).cpu[1]; \
- } while (0)
-
-/* Exclusive disjunction. */
-
-#define ARM_FSET_XOR(DST,F1,F2) \
- do { \
- (DST).cpu[0] = (F1).cpu[0] ^ (F2).cpu[0]; \
- (DST).cpu[1] = (F1).cpu[1] ^ (F2).cpu[1]; \
- } while (0)
-
-/* Difference of feature sets: F1 excluding the elements of F2. */
-
-#define ARM_FSET_EXCLUDE(DST,F1,F2) \
- do { \
- (DST).cpu[0] = (F1).cpu[0] & ~(F2).cpu[0]; \
- (DST).cpu[1] = (F1).cpu[1] & ~(F2).cpu[1]; \
- } while (0)
-
-/* Test for an empty feature set. */
-
-#define ARM_FSET_IS_EMPTY(A) \
- (!((A).cpu[0]) && !((A).cpu[1]))
-
-/* Tests whether the cpu features of A are a subset of B. */
-
-#define ARM_FSET_CPU_SUBSET(A,B) \
- ((((A).cpu[0] & (B).cpu[0]) == (A).cpu[0]) \
- && (((A).cpu[1] & (B).cpu[1]) == (A).cpu[1]))
-
#endif /* GCC_ARM_FLAGS_H */
diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h
index 52c69e9..3de110e 100644
--- a/gcc/config/arm/arm-opts.h
+++ b/gcc/config/arm/arm-opts.h
@@ -32,7 +32,7 @@
enum processor_type
{
#undef ARM_CORE
-#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
+#define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
TARGET_CPU_##INTERNAL_IDENT,
#include "arm-cores.def"
#undef ARM_CORE
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0b82714..822ef14 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -957,7 +957,6 @@ struct processors
const char *arch;
enum base_architecture base_arch;
enum isa_feature isa_bits[isa_num_bits];
- const arm_feature_set flags;
const struct tune_params *const tune;
};
@@ -2292,13 +2291,12 @@ const struct tune_params arm_fa726te_tune =
static const struct processors all_cores[] =
{
/* ARM Cores */
-#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \
+#define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, COSTS) \
{NAME, TARGET_CPU_##IDENT, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
- {ISA isa_nobit}, FLAGS, &arm_##COSTS##_tune},
+ {ISA isa_nobit}, &arm_##COSTS##_tune},
#include "arm-cores.def"
#undef ARM_CORE
- {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit},
- ARM_FSET_EMPTY, NULL}
+ {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
};
static const struct processors all_architectures[] =
@@ -2307,12 +2305,12 @@ static const struct processors all_architectures[] =
/* We don't specify tuning costs here as it will be figured out
from the core. */
-#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS) \
+#define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA) \
{NAME, TARGET_CPU_##CORE, TUNE_FLAGS, #ARCH, BASE_ARCH_##ARCH, \
- {ISA isa_nobit}, FLAGS, NULL},
+ {ISA isa_nobit}, NULL},
#include "arm-arches.def"
#undef ARM_ARCH
- {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, ARM_FSET_EMPTY, NULL}
+ {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, NULL}
};
/* The name of the preprocessor macro to define for this architecture. PROFILE
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 13/21] [arm] Remove FPU rev field
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (17 preceding siblings ...)
2016-12-15 16:08 ` [PATCH 10/21] [arm] Remove remaining references to arm feature sets Richard Earnshaw (lists)
@ 2016-12-15 16:08 ` Richard Earnshaw (lists)
2016-12-15 16:08 ` [PATCH 20/21] [arm] Remove FEATURES field from FPU descriptions Richard Earnshaw (lists)
2016-12-15 16:22 ` [PATCH 17/21] [arm] Use arm_active_target for most FP feature tests Richard Earnshaw (lists)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:08 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1009 bytes --]
Similar to the main ISA, we convert the FPU revision into a set of feature
bits. This permits a more complex set of capability relationships to be
expressed more easily. For now we continue to use the traditional bitmasks.
* arm.h (FPU_FL_VFPv2) New feature bit.
(FPU_FL_VFPv3, FPU_FL_VFPv4, FPU_FL_VFPv5, FPU_FL_ARMv8): Likewise.
(FPU_VFPv2, FPU_VFPv3, FPU_VFPv4, FPU_VFPv5, FPU_ARMv8): New helper
macros.
(FPU_DBL, FPU_D32, FPU_NEON, FPU_CRYPTO, FPU_FP16): Likewise.
(TARGET_FPU_REV): Delete.
(TARGET_VFP3): Use feature bits.
(TARGET_VFP5): Likewise.
(TARGET_FMA): Likewise.
(TARGET_FPU_ARMV8): Likewise.
(struct arm_fpu_desc): Delete rev field.
* arm-fpus.def: Delete REV entry, use new feature bits and macros.
* arm.c (all_fpus): Delete rev field.
---
gcc/config/arm/arm-fpus.def | 44
++++++++++++++++++++++----------------------
gcc/config/arm/arm.c | 4 ++--
gcc/config/arm/arm.h | 28 ++++++++++++++++++++++------
3 files changed, 46 insertions(+), 30 deletions(-)
[-- Attachment #2: 0013-arm-Remove-FPU-rev-field.patch --]
[-- Type: text/x-patch, Size: 5682 bytes --]
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
index eca03bb..25e2ebd 100644
--- a/gcc/config/arm/arm-fpus.def
+++ b/gcc/config/arm/arm-fpus.def
@@ -19,31 +19,31 @@
/* Before using #include to read this file, define a macro:
- ARM_FPU(NAME, REV, FEATURES)
+ ARM_FPU(NAME, FEATURES)
The arguments are the fields of struct arm_fpu_desc.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_FPU("vfp", 2, FPU_FL_DBL)
-ARM_FPU("vfpv2", 2, FPU_FL_DBL)
-ARM_FPU("vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL)
-ARM_FPU("vfpv3-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
-ARM_FPU("vfpv3-d16", 3, FPU_FL_DBL)
-ARM_FPU("vfpv3-d16-fp16", 3, FPU_FL_DBL | FPU_FL_FP16)
-ARM_FPU("vfpv3xd", 3, FPU_FL_NONE)
-ARM_FPU("vfpv3xd-fp16", 3, FPU_FL_FP16)
-ARM_FPU("neon", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON)
-ARM_FPU("neon-vfpv3", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON)
-ARM_FPU("neon-fp16", 3, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
-ARM_FPU("vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
-ARM_FPU("vfpv4-d16", 4, FPU_FL_DBL | FPU_FL_FP16)
-ARM_FPU("fpv4-sp-d16", 4, FPU_FL_FP16)
-ARM_FPU("fpv5-sp-d16", 5, FPU_FL_FP16)
-ARM_FPU("fpv5-d16", 5, FPU_FL_DBL | FPU_FL_FP16)
-ARM_FPU("neon-vfpv4", 4, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
-ARM_FPU("fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_FP16)
-ARM_FPU("neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16)
-ARM_FPU("crypto-neon-fp-armv8", 8, FPU_FL_D32 | FPU_FL_DBL | FPU_FL_NEON | FPU_FL_FP16 | FPU_FL_CRYPTO)
+ARM_FPU("vfp", FPU_VFPv2 | FPU_DBL)
+ARM_FPU("vfpv2", FPU_VFPv2 | FPU_DBL)
+ARM_FPU("vfpv3", FPU_VFPv3 | FPU_D32)
+ARM_FPU("vfpv3-fp16", FPU_VFPv3 | FPU_D32 | FPU_FP16)
+ARM_FPU("vfpv3-d16", FPU_VFPv3 | FPU_DBL)
+ARM_FPU("vfpv3-d16-fp16", FPU_VFPv3 | FPU_DBL | FPU_FP16)
+ARM_FPU("vfpv3xd", FPU_VFPv3)
+ARM_FPU("vfpv3xd-fp16", FPU_VFPv3 | FPU_FP16)
+ARM_FPU("neon", FPU_VFPv3 | FPU_NEON)
+ARM_FPU("neon-vfpv3", FPU_VFPv3 | FPU_NEON)
+ARM_FPU("neon-fp16", FPU_VFPv3 | FPU_NEON | FPU_FP16)
+ARM_FPU("vfpv4", FPU_VFPv4 | FPU_D32 | FPU_FP16)
+ARM_FPU("vfpv4-d16", FPU_VFPv4 | FPU_DBL | FPU_FP16)
+ARM_FPU("fpv4-sp-d16", FPU_VFPv4 | FPU_FP16)
+ARM_FPU("fpv5-sp-d16", FPU_VFPv5 | FPU_FP16)
+ARM_FPU("fpv5-d16", FPU_VFPv5 | FPU_DBL | FPU_FP16)
+ARM_FPU("neon-vfpv4", FPU_VFPv4 | FPU_NEON | FPU_FP16)
+ARM_FPU("fp-armv8", FPU_ARMv8 | FPU_D32 | FPU_FP16)
+ARM_FPU("neon-fp-armv8", FPU_ARMv8 | FPU_NEON | FPU_FP16)
+ARM_FPU("crypto-neon-fp-armv8", FPU_ARMv8 | FPU_CRYPTO | FPU_FP16)
/* Compatibility aliases. */
-ARM_FPU("vfp3", 3, FPU_FL_D32 | FPU_FL_DBL)
+ARM_FPU("vfp3", FPU_VFPv3 | FPU_D32)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 820a6ab..e555cf6 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2323,8 +2323,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
const struct arm_fpu_desc all_fpus[] =
{
-#define ARM_FPU(NAME, REV, FEATURES) \
- { NAME, REV, FEATURES },
+#define ARM_FPU(NAME, FEATURES) \
+ { NAME, FEATURES },
#include "arm-fpus.def"
#undef ARM_FPU
};
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index a412fb1..332f0fa 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -164,10 +164,10 @@ extern tree arm_fp16_type_node;
#define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32)
/* FPU supports VFPv3 instructions. */
-#define TARGET_VFP3 (TARGET_FPU_REV >= 3)
+#define TARGET_VFP3 (TARGET_FPU_FEATURES & FPU_FL_VFPv3)
/* FPU supports FPv5 instructions. */
-#define TARGET_VFP5 (TARGET_FPU_REV >= 5)
+#define TARGET_VFP5 (TARGET_FPU_FEATURES & FPU_FL_VFPv5)
/* FPU only supports VFP single-precision instructions. */
#define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0)
@@ -190,10 +190,10 @@ extern tree arm_fp16_type_node;
(TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5))
/* FPU supports fused-multiply-add operations. */
-#define TARGET_FMA (TARGET_FPU_REV >= 4)
+#define TARGET_FMA (TARGET_FPU_FEATURES & FPU_FL_VFPv4)
/* FPU is ARMv8 compatible. */
-#define TARGET_FPU_ARMV8 (TARGET_FPU_REV >= 8)
+#define TARGET_FPU_ARMV8 (TARGET_FPU_FEATURES & FPU_FL_ARMv8)
/* FPU supports Crypto extensions. */
#define TARGET_CRYPTO \
@@ -341,18 +341,34 @@ typedef unsigned long arm_fpu_feature_set;
#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */
#define FPU_FL_DBL (1u << 3) /* Has double precision. */
#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */
+#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */
+#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */
+#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */
+#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */
+#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */
+
+/* Some useful combinations. */
+#define FPU_VFPv2 (FPU_FL_VFPv2)
+#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3)
+#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4)
+#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5)
+#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8)
+
+#define FPU_DBL (FPU_FL_DBL)
+#define FPU_D32 (FPU_DBL | FPU_FL_D32)
+#define FPU_NEON (FPU_D32 | FPU_FL_NEON)
+#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO)
+#define FPU_FP16 (FPU_FL_FP16)
extern const struct arm_fpu_desc
{
const char *name;
- int rev;
arm_fpu_feature_set features;
} all_fpus[];
/* Accessors. */
#define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name)
-#define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev)
#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
/* Which floating point hardware to schedule for. */
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 20/21] [arm] Remove FEATURES field from FPU descriptions.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (18 preceding siblings ...)
2016-12-15 16:08 ` [PATCH 13/21] [arm] Remove FPU rev field Richard Earnshaw (lists)
@ 2016-12-15 16:08 ` Richard Earnshaw (lists)
2016-12-15 16:22 ` [PATCH 17/21] [arm] Use arm_active_target for most FP feature tests Richard Earnshaw (lists)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:08 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1112 bytes --]
Now that everything uses the new ISA features, we can remove the
FEATURES field from the FPU descriptions, along with all the macros
and definitions associated with it.
* arm-fpus.def (ARM_FPU): Remove features field from all definitions.
* arm.h (arm_fpu_feature_set): Delete typedef.
(FPU_FL_NONE): Delete.
(FPU_FL_NEON): Delete.
(FPU_FL_FP16): Delete.
(FPU_FL_CRYPTO): Delete.
(FPU_FL_DBL): Delete.
(FPU_FL_D32): Delete.
(FPU_FL_VFPv2): Delete.
(FPU_FL_VFPv3): Delete.
(FPU_FL_VFPv4): Delete.
(FPU_FL_VFPv5): Delete.
(FPU_FL_AMRv8): Delete.
(FPU_VFPv2): Delete.
(FPU_VFPv3): Delete.
(FPU_VFPv4): Delete.
(FPU_VFPv5): Delete.
(FPU_ARMv8): Delete.
(FPU_DBL): Delete.
(FPU_D32): Delete.
(FPU_NEON): Delete.
(FPU_CRYPTO): Delete.
(FPU_FP16): Delete.
(arm_fpu_desc): Delete features field.
* arm.c (all_fpus): Don't initialize feature field.
---
gcc/config/arm/arm-fpus.def | 44
++++++++++++++++++++++----------------------
gcc/config/arm/arm.c | 4 ++--
gcc/config/arm/arm.h | 34 ----------------------------------
3 files changed, 24 insertions(+), 58 deletions(-)
[-- Attachment #2: 0020-arm-Remove-FEATURES-field-from-FPU-descriptions.patch --]
[-- Type: text/x-patch, Size: 6164 bytes --]
diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def
index 1be718f..ae8197d 100644
--- a/gcc/config/arm/arm-fpus.def
+++ b/gcc/config/arm/arm-fpus.def
@@ -19,31 +19,31 @@
/* Before using #include to read this file, define a macro:
- ARM_FPU(NAME, ISA, FEATURES)
+ ARM_FPU(NAME, ISA)
The arguments are the fields of struct arm_fpu_desc.
genopt.sh assumes no whitespace up to the first "," in each entry. */
-ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL)
-ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), FPU_VFPv2 | FPU_DBL)
-ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32)
-ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_D32 | FPU_FP16)
-ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL), FPU_VFPv3 | FPU_DBL)
-ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_DBL | FPU_FP16)
-ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3), FPU_VFPv3)
-ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_FP16)
-ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON)
-ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON), FPU_VFPv3 | FPU_NEON)
-ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv), FPU_VFPv3 | FPU_NEON | FPU_FP16)
-ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32), FPU_VFPv4 | FPU_D32 | FPU_FP16)
-ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON), FPU_VFPv4 | FPU_NEON | FPU_FP16)
-ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL), FPU_VFPv4 | FPU_DBL | FPU_FP16)
-ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4), FPU_VFPv4 | FPU_FP16)
-ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5), FPU_VFPv5 | FPU_FP16)
-ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL), FPU_VFPv5 | FPU_DBL | FPU_FP16)
-ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32), FPU_ARMv8 | FPU_D32 | FPU_FP16)
-ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON), FPU_ARMv8 | FPU_NEON | FPU_FP16)
-ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO), FPU_ARMv8 | FPU_CRYPTO | FPU_FP16)
+ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3))
+ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
+ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON))
+ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv))
+ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON))
+ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4))
+ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5))
+ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL))
+ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32))
+ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON))
+ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO))
/* Compatibility aliases. */
-ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32), FPU_VFPv3 | FPU_D32)
+ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 1d3bb89..522989d 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2328,8 +2328,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__";
const struct arm_fpu_desc all_fpus[] =
{
-#define ARM_FPU(NAME, ISA, FEATURES) \
- { NAME, {ISA isa_nobit}, FEATURES },
+#define ARM_FPU(NAME, ISA) \
+ { NAME, {ISA isa_nobit} },
#include "arm-fpus.def"
#undef ARM_FPU
};
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 17f030b..4582d2e 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -326,44 +326,10 @@ extern tree arm_fp16_type_node;
{"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \
{"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},
-/* FPU feature sets. */
-
-typedef unsigned long arm_fpu_feature_set;
-
-/* Test for an FPU feature. */
-#define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F))
-
-/* FPU Features. */
-#define FPU_FL_NONE (0u)
-#define FPU_FL_NEON (1u << 0) /* NEON instructions. */
-#define FPU_FL_FP16 (1u << 1) /* Half-precision. */
-#define FPU_FL_CRYPTO (1u << 2) /* Crypto extensions. */
-#define FPU_FL_DBL (1u << 3) /* Has double precision. */
-#define FPU_FL_D32 (1u << 4) /* Has 32 double precision regs. */
-#define FPU_FL_VFPv2 (1u << 5) /* Has VFPv2 features. */
-#define FPU_FL_VFPv3 (1u << 6) /* Has VFPv3 extensions. */
-#define FPU_FL_VFPv4 (1u << 7) /* Has VFPv4 extensions. */
-#define FPU_FL_VFPv5 (1u << 8) /* Has VFPv5 extensions. */
-#define FPU_FL_ARMv8 (1u << 9) /* Has ARMv8 extensions to VFP. */
-
-/* Some useful combinations. */
-#define FPU_VFPv2 (FPU_FL_VFPv2)
-#define FPU_VFPv3 (FPU_VFPv2 | FPU_FL_VFPv3)
-#define FPU_VFPv4 (FPU_VFPv3 | FPU_FL_VFPv4)
-#define FPU_VFPv5 (FPU_VFPv4 | FPU_FL_VFPv5)
-#define FPU_ARMv8 (FPU_VFPv5 | FPU_FL_ARMv8)
-
-#define FPU_DBL (FPU_FL_DBL)
-#define FPU_D32 (FPU_DBL | FPU_FL_D32)
-#define FPU_NEON (FPU_D32 | FPU_FL_NEON)
-#define FPU_CRYPTO (FPU_NEON | FPU_FL_CRYPTO)
-#define FPU_FP16 (FPU_FL_FP16)
-
extern const struct arm_fpu_desc
{
const char *name;
enum isa_feature isa_bits[isa_num_bits];
- arm_fpu_feature_set features;
} all_fpus[];
/* Which floating point hardware to schedule for. */
^ permalink raw reply [flat|nested] 21+ messages in thread* [PATCH 17/21] [arm] Use arm_active_target for most FP feature tests.
[not found] <cover.1481814793.git.Richard.Earnshaw@arm.com>
` (19 preceding siblings ...)
2016-12-15 16:08 ` [PATCH 20/21] [arm] Remove FEATURES field from FPU descriptions Richard Earnshaw (lists)
@ 2016-12-15 16:22 ` Richard Earnshaw (lists)
20 siblings, 0 replies; 21+ messages in thread
From: Richard Earnshaw (lists) @ 2016-12-15 16:22 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 748 bytes --]
Now that the isa feature bits are all available in arm_active_target
we can use that for most of the feature tests that are needed.
* arm.h (TARGET_VFPD32): Use arm_active_target.
(TARGET_VFP3): Likewise.
(TARGET_VFP5): Likewise.
(TARGET_VFP_SINGLE): Likewise.
(TARGET_VFP_DOUBLE): Likewise.
(TARGET_NEON_FP16): Likewise.
(TARGET_FP16): Likewise.
(TARGET_FMA): Likewise.
(TARGET_FPU_ARMV8): Likewise.
(TARGET_CRYPTO): Likewise.
(TARGET_NEON): Likewise.
(TARGET_FPU_FEATURES): Delete.
* arm.c (arm_option_check_internal): Check for iwmmxt conflict with
Neon using arm_active_target.
---
gcc/config/arm/arm.c | 3 +--
gcc/config/arm/arm.h | 33 ++++++++++++++-------------------
2 files changed, 15 insertions(+), 21 deletions(-)
[-- Attachment #2: 0017-arm-Use-arm_active_target-for-most-FP-feature-tests.patch --]
[-- Type: text/x-patch, Size: 4077 bytes --]
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index df7a3ea..676c78b 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -2815,11 +2815,10 @@ static void
arm_option_check_internal (struct gcc_options *opts)
{
int flags = opts->x_target_flags;
- const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index];
/* iWMMXt and NEON are incompatible. */
if (TARGET_IWMMXT
- && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON))
+ && bitmap_bit_p (arm_active_target.isa, isa_bit_neon))
error ("iWMMXt and NEON are incompatible");
/* Make sure that the processor choice does not conflict with any of the
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 980bb74..17f030b 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -161,28 +161,27 @@ extern tree arm_fp16_type_node;
to be more careful with TARGET_NEON as noted below. */
/* FPU is has the full VFPv3/NEON register file of 32 D registers. */
-#define TARGET_VFPD32 (TARGET_FPU_FEATURES & FPU_FL_D32)
+#define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32))
/* FPU supports VFPv3 instructions. */
-#define TARGET_VFP3 (TARGET_FPU_FEATURES & FPU_FL_VFPv3)
+#define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv3))
/* FPU supports FPv5 instructions. */
-#define TARGET_VFP5 (TARGET_FPU_FEATURES & FPU_FL_VFPv5)
+#define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_FPv5))
/* FPU only supports VFP single-precision instructions. */
-#define TARGET_VFP_SINGLE ((TARGET_FPU_FEATURES & FPU_FL_DBL) == 0)
+#define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE)
/* FPU supports VFP double-precision instructions. */
-#define TARGET_VFP_DOUBLE (TARGET_FPU_FEATURES & FPU_FL_DBL)
+#define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl))
/* FPU supports half-precision floating-point with NEON element load/store. */
#define TARGET_NEON_FP16 \
- (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON) \
- && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+ (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \
+ && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv))
-/* FPU supports VFP half-precision floating-point. */
-#define TARGET_FP16 \
- (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16))
+/* FPU supports VFP half-precision floating-point conversions. */
+#define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv))
/* FPU supports converting between HFmode and DFmode in a single hardware
step. */
@@ -190,14 +189,14 @@ extern tree arm_fp16_type_node;
(TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5))
/* FPU supports fused-multiply-add operations. */
-#define TARGET_FMA (TARGET_FPU_FEATURES & FPU_FL_VFPv4)
+#define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4))
/* FPU is ARMv8 compatible. */
-#define TARGET_FPU_ARMV8 (TARGET_FPU_FEATURES & FPU_FL_ARMv8)
+#define TARGET_FPU_ARMV8 \
+ (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8))
/* FPU supports Crypto extensions. */
-#define TARGET_CRYPTO \
- (ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO))
+#define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto))
/* FPU supports Neon instructions. The setting of this macro gets
revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT
@@ -205,7 +204,7 @@ extern tree arm_fp16_type_node;
available. */
#define TARGET_NEON \
(TARGET_32BIT && TARGET_HARD_FLOAT \
- && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON))
+ && bitmap_bit_p (arm_active_target.isa, isa_bit_neon))
/* FPU supports ARMv8.1 Adv.SIMD extensions. */
#define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1)
@@ -367,10 +366,6 @@ extern const struct arm_fpu_desc
arm_fpu_feature_set features;
} all_fpus[];
-/* Accessors. */
-
-#define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features)
-
/* Which floating point hardware to schedule for. */
extern int arm_fpu_attr;
^ permalink raw reply [flat|nested] 21+ messages in thread