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From: Xi Ruoyao To: chenglulu , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn Date: Fri, 05 Jan 2024 22:16:25 +0800 In-Reply-To: References: <20240105034021.30177-1-chenglulu@loongson.cn> <20240105034021.30177-3-chenglulu@loongson.cn> <0fe0f370-a593-d060-d260-0e190986f833@loongson.cn> <4cdfda6960e75ccc6ccea6263ac02e79c9dba572.camel@xry111.site> <74482b5cbfef5a9d07185cd63430b3907fb389d1.camel@xry111.site> Autocrypt: addr=xry111@xry111.site; prefer-encrypt=mutual; keydata=mDMEYnkdPhYJKwYBBAHaRw8BAQdAsY+HvJs3EVKpwIu2gN89cQT/pnrbQtlvd6Yfq7egugi0HlhpIFJ1b3lhbyA8eHJ5MTExQHhyeTExMS5zaXRlPoiTBBMWCgA7FiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwMFCwkIBwICIgIGFQoJCAsCBBYCAwECHgcCF4AACgkQrKrSDhnnEOPHFgD8D9vUToTd1MF5bng9uPJq5y3DfpcxDp+LD3joA3U2TmwA/jZtN9xLH7CGDHeClKZK/ZYELotWfJsqRcthOIGjsdAPuDgEYnkdPhIKKwYBBAGXVQEFAQEHQG+HnNiPZseiBkzYBHwq/nN638o0NPwgYwH70wlKMZhRAwEIB4h4BBgWCgAgFiEEkdD1djAfkk197dzorKrSDhnnEOMFAmJ5HT4CGwwACgkQrKrSDhnnEOPjXgD/euD64cxwqDIqckUaisT3VCst11RcnO5iRHm6meNIwj0BALLmWplyi7beKrOlqKfuZtCLbiAPywGfCNg8LOTt4iMD Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.50.2 MIME-Version: 1.0 X-Spam-Status: No, score=-6.5 required=5.0 tests=BAYES_00,BODY_8BITS,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,LIKELY_SPAM_FROM,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Fri, 2024-01-05 at 20:45 +0800, chenglulu wrote: >=20 > =E5=9C=A8 2024/1/5 =E4=B8=8B=E5=8D=887:55, Xi Ruoyao =E5=86=99=E9=81=93: > > On Fri, 2024-01-05 at 18:25 +0800, Xi Ruoyao wrote: > > > On Fri, 2024-01-05 at 17:57 +0800, chenglulu wrote: > > > > =E5=9C=A8 2024/1/5 =E4=B8=8B=E5=8D=884:37, Xi Ruoyao =E5=86=99=E9= =81=93: > > > > > On Fri, 2024-01-05 at 11:40 +0800, Lulu Cheng wrote: > > > > > > =C2=A0=C2=A0=C2=A0bool > > > > > > =C2=A0=C2=A0=C2=A0loongarch_explicit_relocs_p (enum loongarch_s= ymbol_type type) > > > > > > =C2=A0=C2=A0=C2=A0{ > > > > > > +=C2=A0 /* Instructions pcalau12i, addi.d, lu32i.d and lu52i.d = must be adjancent > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0 so that the linker can infer the PC o= f pcalau12i to apply relocations > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0 to lu32i.d and lu52i.d.=C2=A0 Otherwi= se, the results would be incorrect if > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0 these four instructions are not in th= e same 4KiB page. > > > > > > +=C2=A0=C2=A0=C2=A0=C2=A0 Therefore, macro instructions are use= d when cmodel=3Dextreme.=C2=A0 */ > > > > > > +=C2=A0 if (loongarch_symbol_extreme_p (type)) > > > > > > +=C2=A0=C2=A0=C2=A0 return false; > > > > > I think this is a bit of strange.=C2=A0 With -mexplicit-relocs=3D= {auto,always} > > > > > we should still use explicit relocs, but coding all 4 instruction= s > > > > > altogether as > > > > >=20 > > > > > "pcalau12i.d\t%1,%pc64_hi12(%2)\n\taddi.d\t%0,$r0,%pclo12(%2)\n\t= lu32i.d\t%0,%pc64_lo20(%2)\n\tlu52i.d\t%0,%0,%pc64_hi12(%2)" > > > > >=20 > > > > > Give me several hours trying to implement this... > > > > >=20 > > > > I think there is no difference between macros and these instruction= s put > > > > together. If implement it in a split form, I think I can try it thr= ough > > > > TARGET_SCHED_MACRO_FUSION_PAIR_P > > We don't need to split the insn.=C2=A0 We can just add a "large insn" > > containing the assembly output we want. > >=20 > > See the attached patch.=C2=A0 Note that TLS LE/LD/GD needs a fix too be= cause > > they are basically an variation of GOT addressing. > >=20 > > I've ran some small tests and now trying to bootstrap GCC with - > > mcmodel=3Dextreme in BOOT_CFLAGS... > >=20 > > > There is a difference: > > >=20 > > > int x; > > > int t() { return x; } > > >=20 > > > pcalau12i.d t0, %pc_hi20(x) > > > addi.d t1, r0, %pc_lo12(x) > > > lu32i.d t1, %pc64_lo20(x) > > > lu52i.d t1, t1, %pc64_hi12(x) > > > ldx.w a0, t0, t1 > > >=20 > > > is slightly better than > > >=20 > > > pcalau12i.d t0, %pc_hi20(x) > > > addi.d t1, r0, %pc_lo12(x) > > > lu32i.d t1, %pc64_lo20(x) > > > lu52i.d t1, t1, %pc64_hi12(x) > > > addi.d t0, t0, t1 > > > ld.w a0, t0, 0 > > >=20 > > > And generating macros when -mexplicit-relocs=3Dalways can puzzle peop= le > > > (it says "always" :-\ ). > > >=20 > Thumbs up! This method is much better than my method, I learned=20 > something! grateful! > But I still have to test the accuracy. I found an issue bootstrapping GCC with -mcmodel=3Dextreme in BOOT_CFLAGS: we need a target hook to tell the generic code UNSPEC_LA_PCREL_64_PART{1,2} are just a wrapper around symbols, or we'll see millions lines of messages like ../../gcc/gcc/tree.h:4171:1: note: non-delegitimized UNSPEC UNSPEC_LA_PCREL_64_PART1 (42) found in variable location diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loong= arch.cc index 4f89c4af323..410e1b5e693 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -10868,6 +10868,24 @@ loongarch_asm_code_end (void) #undef DUMP_FEATURE } =20 +static rtx loongarch_delegitimize_address (rtx op) +{ + if (GET_CODE (op) =3D=3D UNSPEC) + { + int unspec =3D XINT (op, 1); + switch (unspec) + { + case UNSPEC_LA_PCREL_64_PART1: + case UNSPEC_LA_PCREL_64_PART2: + return XVECEXP (op, 0, 0); + default: + return op; + } + } + + return op; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" @@ -11129,6 +11147,10 @@ loongarch_asm_code_end (void) #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \ loongarch_builtin_support_vector_misalignment =20 +#undef TARGET_DELEGITIMIZE_ADDRESS +#define TARGET_DELEGITIMIZE_ADDRESS \ + loongarch_delegitimize_address + struct gcc_target targetm =3D TARGET_INITIALIZER; =20 #include "gt-loongarch.h" --=20 Xi Ruoyao School of Aerospace Science and Technology, Xidian University