From: "Jie Mei" <jie.mei@oss.cipunited.com>
To: <gcc-patches@gcc.gnu.org>
Subject: [PATCH 0/8] MIPS: Add MIPS16e2 ASE instrucions.
Date: Fri, 05 May 2023 17:41:31 +0800 [thread overview]
Message-ID: <cover.1683273171.git.jie.mei@oss.cipunited.com> (raw)
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The MIPS16e2 ASE is an enhancement to the MIPS16e ASE,
which includes all MIPS16e instructions, with some addition.
This series of patches adds all instructions of MIPS16E2 ASE.
Jie Mei (8):
MIPS: Add basic support for mips16e2
MIPS: Add MOVx instructions support for mips16e2
MIPS: Add instruction about global pointer register for mips16e2
MIPS: Add bitwise instructions for mips16e2
MIPS: Add LUI instruction for mips16e2
MIPS: Add load/store word left/right instructions for mips16e2
MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2
MIPS: Add CACHE instruction for mips16e2
gcc/config/mips/constraints.md | 4 +
gcc/config/mips/mips-protos.h | 4 +
gcc/config/mips/mips.cc | 164 ++++++++++--
gcc/config/mips/mips.h | 32 ++-
gcc/config/mips/mips.md | 188 ++++++++++++--
gcc/config/mips/mips.opt | 4 +
gcc/config/mips/predicates.md | 19 +-
gcc/doc/invoke.texi | 7 +
gcc/testsuite/gcc.target/mips/mips.exp | 10 +
.../gcc.target/mips/mips16e2-cache.c | 34 +++
gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++
gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++
gcc/testsuite/gcc.target/mips/mips16e2.c | 240 ++++++++++++++++++
13 files changed, 816 insertions(+), 59 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c
create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c
create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c
create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2.c
--
2.40.1
next reply other threads:[~2023-05-05 9:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 9:41 Jie Mei [this message]
2023-05-05 9:41 ` [PATCH 1/8] MIPS: Add basic support for mips16e2 Jie Mei
2023-05-05 9:41 ` [PATCH 2/8] MIPS: Add MOVx instructions " Jie Mei
2023-05-05 9:41 ` [PATCH 3/8] MIPS: Add instruction about global pointer register " Jie Mei
2023-05-05 9:41 ` [PATCH 4/8] MIPS: Add bitwise instructions " Jie Mei
2023-05-05 9:41 ` [PATCH 5/8] MIPS: Add LUI instruction " Jie Mei
2023-05-05 9:41 ` [PATCH 6/8] MIPS: Add load/store word left/right instructions " Jie Mei
2023-05-05 9:41 ` [PATCH 7/8] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT " Jie Mei
2023-05-05 9:41 ` [PATCH 8/8] MIPS: Add CACHE instruction " Jie Mei
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