From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.35]) by sourceware.org (Postfix) with UTF8SMTPS id 152443858413 for ; Fri, 12 May 2023 06:19:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 152443858413 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1683872336; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=Ui4c1Iv2SIPBU9mPjhy0fib8pdwMnfpdhp/UPzM8wqs=; b=R+BQ3yghWhAMYE1XTrlFNvV2/a2ExDuZWbrRUoGQE916L2yRLZO5dFGHhnaAYUuhmgiBma yzEfV8I+Warin9Of1k71fOMFKh+5F9N2CXj2SwxRWJrwDzGL7W33zutULvcpaW4LLit3RJ MZhp2cUtQFSfGzdGZArlckwlu2czGFstN9c0Lm+lW1Nm16rNjJh481B8aQYsNyUprGhQSt JJMbSZcfAtVGG8Zp/eWkUuZWmQeABjFW4mbusrkOYVEpwEiw9thWGY8VbXA7ZL4E6fSI7f 6vuHPy48y5p2J7vUdDU9kGmMySOYiqLTxUmEzFCLI/v9tYa5JWWzncgtpqS4YQ== Date: Fri, 12 May 2023 14:18:46 +0800 Message-Id: Mime-Version: 1.0 X-Mailer: git-send-email 2.40.1 Content-Transfer-Encoding: 8bit Content-Type: multipart/alternative; boundary=08a50d18ffda385f4ded49d71960882484784a81cf9fb3b5cdd176d86f22 To: From: "Jie Mei" Subject: [PATCH v2 0/9] MIPS: Add MIPS16e2 ASE instrucions. X-Lms-Return-Path: X-Spam-Status: No, score=-6.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,HTML_MESSAGE,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --08a50d18ffda385f4ded49d71960882484784a81cf9fb3b5cdd176d86f22 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. This series of patches adds all instructions of MIPS16E2 ASE. Jie Mei (9): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add instruction about global pointer register for mips16e2 MIPS: Add bitwise instructions for mips16e2 MIPS: Add LUI instruction for mips16e2 MIPS: Add load/store word left/right instructions for mips16e2 MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 MIPS: Add CACHE instruction for mips16e2 MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions gcc/config/mips/constraints.md | 4 + gcc/config/mips/mips-protos.h | 4 + gcc/config/mips/mips.cc | 164 ++++++++++-- gcc/config/mips/mips.h | 32 ++- gcc/config/mips/mips.md | 200 ++++++++++++--- gcc/config/mips/mips.opt | 4 + gcc/config/mips/predicates.md | 21 +- gcc/doc/invoke.texi | 7 + gcc/testsuite/gcc.target/mips/mips.exp | 10 + .../gcc.target/mips/mips16e2-cache.c | 34 +++ gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++ gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++ gcc/testsuite/gcc.target/mips/mips16e2.c | 240 ++++++++++++++++++ 13 files changed, 825 insertions(+), 64 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2.c --=20 2.40.1= --08a50d18ffda385f4ded49d71960882484784a81cf9fb3b5cdd176d86f22--