From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.31]) by sourceware.org (Postfix) with UTF8SMTPS id C08CC3856DDC for ; Wed, 24 May 2023 09:41:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C08CC3856DDC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1684921271; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=xAl0K3YzR3aQ51YCSmVK1A5c0UAbRbWEZMVkZY3Pk3U=; b=Z2uu3I8r8876RDdiJCq0P9g/da4W5WnFb2AT96RIT8w6EaAq1ALw8cnwbrddFszUZCFFpr MR1HJ4WmQqrKthD51J6oHodZUcP0WnFvkKjrXzYZ7bsiCOyDHfW2UgeqgTdwEdPFd5tsDa qFx7+RfRgsEibPk6Re8iTaT4DhHCuGvu4k/JscP3uz+nd0SfcVVad7idsPmFonur+b/3tN gWWQqhPtHmu3rbUZ4boWw8zhorzvxnilpOZUH9wwTWj3ecFrdhTzEd0C4QcGAfWoy7NcZt jcGmluYteZSE6OB7Di0gSR3mY9yBCnfAba1BLIaibmUdH+QnZs3bfLWEUavZBg== Mime-Version: 1.0 Content-Transfer-Encoding: 8bit To: Message-Id: Content-Type: multipart/alternative; boundary=c16cb2e7b8237b3c14d4b86ad5342dce14a187985eb503aa56505d9eb593 X-Mailer: git-send-email 2.40.1 X-Lms-Return-Path: Cc: "YunQiang Su" , "Maciej W . Rozycki" From: "Jie Mei" Subject: [PATCH v3 0/9] MIPS: Add MIPS16e2 ASE instrucions. Date: Wed, 24 May 2023 17:41:10 +0800 X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIM_INVALID,DKIM_SIGNED,HTML_MESSAGE,KAM_DMARC_STATUS,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --c16cb2e7b8237b3c14d4b86ad5342dce14a187985eb503aa56505d9eb593 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Patch V2: adds new patch. Patch V3: `%{mmips16e2} \` puts the wrong palce in first patch, V3 fix it. The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. This series of patches adds all instructions from MIPS16E2 ASE with corresponding tests. Jie Mei (9): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add instruction about global pointer register for mips16e2 MIPS: Add bitwise instructions for mips16e2 MIPS: Add LUI instruction for mips16e2 MIPS: Add load/store word left/right instructions for mips16e2 MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 MIPS: Add CACHE instruction for mips16e2 MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions gcc/config/mips/constraints.md | 4 + gcc/config/mips/mips-protos.h | 4 + gcc/config/mips/mips.cc | 164 ++++++++++-- gcc/config/mips/mips.h | 32 ++- gcc/config/mips/mips.md | 200 ++++++++++++--- gcc/config/mips/mips.opt | 4 + gcc/config/mips/predicates.md | 21 +- gcc/doc/invoke.texi | 7 + gcc/testsuite/gcc.target/mips/mips.exp | 10 + .../gcc.target/mips/mips16e2-cache.c | 34 +++ gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++ gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++ gcc/testsuite/gcc.target/mips/mips16e2.c | 240 ++++++++++++++++++ 13 files changed, 825 insertions(+), 64 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2.c --=20 2.40.1= --c16cb2e7b8237b3c14d4b86ad5342dce14a187985eb503aa56505d9eb593--