From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t03.bc.larksuite.com (t03.bc.larksuite.com [209.127.231.36]) by sourceware.org (Postfix) with UTF8SMTPS id 2AF773858414 for ; Mon, 19 Jun 2023 08:31:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2AF773858414 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=feishu2303200042; d=oss.cipunited.com; t=1687163481; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=mBLnAmtC3qobbDPoDT7TKsZ1ey+l60v6W+PRcaZp3+o=; b=l7N8Fblp+X/iaiUu6myZlvGnQDgxFDDkEfj86jqE1zKZbG8Qw64P5+yz6Nskf+8oVa0kjz +qX2t2SJ6TPEoFadRxRq3oLdUJ6X9gwxSDu5F9RNfIZMWBSc0RcfxU6voj0CTuSK8+yvpY xhiRz9Q9lzHyJ4g27DXH5y0/aoP00G4bJaijiP4hi/Wqgs4BavpvD/4fVHSKjI0z8/7NeJ sJbroY4mVRpb9KYj0+E8tYjWObO5fh7qUE49owSK23JwUOFoVzk/6FRjv1awDlO/qGh6BN 2M4jSJezBquDsMYmhQJl7/GtBsHsdnxQcDHjk2iMf2qfcHqJpjsrJYjOHZgGsw== Message-Id: To: Cc: "YunQiang Su" , "Maciej W . Rozycki" Mime-Version: 1.0 X-Mailer: git-send-email 2.40.1 From: "Jie Mei" Subject: [PATCH v4 0/9] MIPS: Add MIPS16e2 ASE instrucions. Date: Mon, 19 Jun 2023 16:29:49 +0800 X-Lms-Return-Path: Content-Transfer-Encoding: 8bit Content-Type: multipart/alternative; boundary=093df5f056a499fb3e1d0e9cc6bd65dfe40a57328bef6a32327db24fad68 X-Spam-Status: No, score=-5.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HTML_MESSAGE,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --093df5f056a499fb3e1d0e9cc6bd65dfe40a57328bef6a32327db24fad68 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Patch V2: adds new patch. Patch V3: `%{mmips16e2} \` puts the wrong palce in first patch, V3 fix it. Patch V4: fixed style error for the patch. The MIPS16e2 ASE is an enhancement to the MIPS16e ASE, which includes all MIPS16e instructions, with some addition. This series of patches adds all instructions from MIPS16E2 ASE with corresponding tests. Jie Mei (9): MIPS: Add basic support for mips16e2 MIPS: Add MOVx instructions support for mips16e2 MIPS: Add instruction about global pointer register for mips16e2 MIPS: Add bitwise instructions for mips16e2 MIPS: Add LUI instruction for mips16e2 MIPS: Add load/store word left/right instructions for mips16e2 MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 MIPS: Add CACHE instruction for mips16e2 MIPS: Make mips16e2 generating ZEB/ZEH instead of ANDI under certain conditions gcc/config/mips/constraints.md | 4 + gcc/config/mips/mips-protos.h | 4 + gcc/config/mips/mips.cc | 164 ++++++++++-- gcc/config/mips/mips.h | 33 ++- gcc/config/mips/mips.md | 200 ++++++++++++--- gcc/config/mips/mips.opt | 4 + gcc/config/mips/predicates.md | 21 +- gcc/doc/invoke.texi | 7 + gcc/testsuite/gcc.target/mips/mips.exp | 10 + .../gcc.target/mips/mips16e2-cache.c | 34 +++ gcc/testsuite/gcc.target/mips/mips16e2-cmov.c | 68 +++++ gcc/testsuite/gcc.target/mips/mips16e2-gp.c | 101 ++++++++ gcc/testsuite/gcc.target/mips/mips16e2.c | 240 ++++++++++++++++++ 13 files changed, 826 insertions(+), 64 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cache.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-cmov.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2-gp.c create mode 100644 gcc/testsuite/gcc.target/mips/mips16e2.c --=20 2.40.1= --093df5f056a499fb3e1d0e9cc6bd65dfe40a57328bef6a32327db24fad68--