* [RFC PATCH] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
@ 2023-08-30 6:44 Tsukasa OI
2023-08-30 22:54 ` [RFC PATCH v2 0/1] " Tsukasa OI
0 siblings, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2023-08-30 6:44 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.
And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).
* czero.eqz == vt.maskc
* czero.nez == vt.maskcn
This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support. With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.
The specification for the 'XVentanaCondOps' extension is based on:
<https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero.<eqz>.<GPR><X>): Ditto.
(*czero.eqz.<GPR><X>.opt1): Ditto.
(*czero.nez.<GPR><X>.opt2): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
modified from zicond-primitiveSemantics.c.
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
from zicond-xor-01.c.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 53 +++++++++++++++----
.../xventanacondops-primitiveSemantics-rv32.c | 45 ++++++++++++++++
.../xventanacondops-primitiveSemantics.c | 48 +++++++++++++++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++
9 files changed, 163 insertions(+), 14 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5ed69abd214d..a4fb0a0a5946 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -319,6 +319,12 @@ enum riscv_entity
#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
+#define MASK_XVENTANACONDOPS (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) != 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
+
/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 2b39a6167442..a3285985e43f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2725,7 +2725,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& outer_code == SET
&& ((GET_CODE (XEXP (x, 1)) == REG
&& XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
@@ -3822,7 +3822,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
cond, cons, alt)));
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& GET_MODE_CLASS (mode) == MODE_INT)
{
/* The comparison must be comparing WORD_MODE objects. We must
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0127b9e5abbd..0f61199f1747 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2577,7 +2577,7 @@
(if_then_else:GPR (match_operand 1 "comparison_operator")
(match_operand:GPR 2 "sfb_alu_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE"
{
if (riscv_expand_conditional_move (operands[0], operands[1],
operands[2], operands[3]))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index d2407c3c5021..a3bb3ad3089d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -257,6 +257,9 @@ int riscv_ztso_subext
TargetVariable
int riscv_xthead_subext
+TargetVariable
+int riscv_xventana_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 4619220ef8ac..9c2f470668ac 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -1,4 +1,5 @@
-;; Machine description for the RISC-V Zicond extension
+;; Machine description for the RISC-V Zicond extension and functionally-
+;; equivalent XVentanaCondOps vendor extension
;; Copyright (C) 2022-23 Free Software Foundation, Inc.
;; This file is part of GCC.
@@ -20,6 +21,8 @@
(define_code_iterator eq_or_ne [eq ne])
(define_code_attr eqz [(eq "nez") (ne "eqz")])
(define_code_attr nez [(eq "eqz") (ne "nez")])
+(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")])
+(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")])
;; Zicond
(define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
@@ -28,8 +31,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "r")
(const_int 0)))]
- "TARGET_ZICOND"
- "czero.<eqz>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<eqz>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.<eqz_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.<nez>.<GPR:mode><X:mode>"
@@ -38,8 +48,15 @@
(const_int 0))
(const_int 0)
(match_operand:GPR 2 "register_operand" "r")))]
- "TARGET_ZICOND"
- "czero.<nez>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<nez>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.<nez_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Special optimization under eq/ne in primitive semantics
@@ -49,8 +66,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "1")
(match_operand:GPR 3 "register_operand" "r")))]
- "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
- "czero.eqz\t%0,%3,%1"
+ "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])"
+ {
+ if (TARGET_ZICOND)
+ return "czero.eqz\t%0,%3,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc\t%0,%3,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
@@ -59,8 +83,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "r")
(match_operand:GPR 3 "register_operand" "1")))]
- "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
- "czero.nez\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[3])"
+ {
+ if (TARGET_ZICOND)
+ return "czero.nez\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskcn\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Combine creates this form in some cases (particularly the coremark
@@ -72,7 +103,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && TARGET_ZBS"
+ "TARGET_ZICOND_LIKE && TARGET_ZBS"
[(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
@@ -85,7 +116,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
[(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
new file mode 100644
index 000000000000..992f1425c54f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */
+/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
new file mode 100644
index 000000000000..04947de6156b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
+/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
new file mode 100644
index 000000000000..c2f0dc041cb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long xor1(long crc, long poly)
+{
+ if (crc & 1)
+ crc ^= poly;
+
+ return crc;
+}
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */
+/* { dg-final { scan-assembler-times "xor\t" 1 } } */
base-commit: a248e1cc860821b96a42be96478257c4964a7c2a
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [RFC PATCH v2 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-08-30 6:44 [RFC PATCH] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support Tsukasa OI
@ 2023-08-30 22:54 ` Tsukasa OI
2023-08-30 22:54 ` [RFC PATCH v2 1/1] " Tsukasa OI
2023-09-05 12:10 ` [PATCH v3 0/1] " Tsukasa OI
0 siblings, 2 replies; 12+ messages in thread
From: Tsukasa OI @ 2023-08-30 22:54 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
PATCH v1:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628786.html>
Changes: v1 -> v2
* Removed bogus opt2 pattern as pointed out in:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628867.html>
note that this is not in the ChangeLog expecting the patch above
applies first.
Tsukasa OI (1):
RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 52 ++++++++++++-------
.../xventanacondops-primitiveSemantics-rv32.c | 45 ++++++++++++++++
.../xventanacondops-primitiveSemantics.c | 48 +++++++++++++++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++
9 files changed, 154 insertions(+), 22 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
base-commit: 597b9ec69bca8acb7a3d65641c0a730de8b27ed4
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [RFC PATCH v2 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-08-30 22:54 ` [RFC PATCH v2 0/1] " Tsukasa OI
@ 2023-08-30 22:54 ` Tsukasa OI
2023-09-05 12:10 ` [PATCH v3 0/1] " Tsukasa OI
1 sibling, 0 replies; 12+ messages in thread
From: Tsukasa OI @ 2023-08-30 22:54 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.
And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).
* czero.eqz == vt.maskc
* czero.nez == vt.maskcn
This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support. With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.
The specification for the 'XVentanaCondOps' extension is based on:
<https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero.<eqz>.<GPR><X>): Ditto.
(*czero.eqz.<GPR><X>.opt1): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
modified from zicond-primitiveSemantics.c.
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
from zicond-xor-01.c.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 52 ++++++++++++-------
.../xventanacondops-primitiveSemantics-rv32.c | 45 ++++++++++++++++
.../xventanacondops-primitiveSemantics.c | 48 +++++++++++++++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++
9 files changed, 154 insertions(+), 22 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5ed69abd214d..a4fb0a0a5946 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -319,6 +319,12 @@ enum riscv_entity
#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
+#define MASK_XVENTANACONDOPS (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) != 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
+
/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5dc303f89c79..89af39a08190 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2744,7 +2744,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& outer_code == SET
&& ((GET_CODE (XEXP (x, 1)) == REG
&& XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
@@ -3841,7 +3841,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
cond, cons, alt)));
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& GET_MODE_CLASS (mode) == MODE_INT)
{
/* The comparison must be comparing WORD_MODE objects. We must
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4041875e0e35..29ce75cf280c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2580,7 +2580,7 @@
(if_then_else:GPR (match_operand 1 "comparison_operator")
(match_operand:GPR 2 "sfb_alu_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE"
{
if (riscv_expand_conditional_move (operands[0], operands[1],
operands[2], operands[3]))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index d2407c3c5021..a3bb3ad3089d 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -257,6 +257,9 @@ int riscv_ztso_subext
TargetVariable
int riscv_xthead_subext
+TargetVariable
+int riscv_xventana_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 4619220ef8ac..404fbebabf08 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -1,4 +1,5 @@
-;; Machine description for the RISC-V Zicond extension
+;; Machine description for the RISC-V Zicond extension and functionally-
+;; equivalent XVentanaCondOps vendor extension
;; Copyright (C) 2022-23 Free Software Foundation, Inc.
;; This file is part of GCC.
@@ -20,6 +21,8 @@
(define_code_iterator eq_or_ne [eq ne])
(define_code_attr eqz [(eq "nez") (ne "eqz")])
(define_code_attr nez [(eq "eqz") (ne "nez")])
+(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")])
+(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")])
;; Zicond
(define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
@@ -28,8 +31,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "r")
(const_int 0)))]
- "TARGET_ZICOND"
- "czero.<eqz>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<eqz>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.<eqz_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.<nez>.<GPR:mode><X:mode>"
@@ -38,8 +48,15 @@
(const_int 0))
(const_int 0)
(match_operand:GPR 2 "register_operand" "r")))]
- "TARGET_ZICOND"
- "czero.<nez>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<nez>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.<nez_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Special optimization under eq/ne in primitive semantics
@@ -49,18 +66,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "1")
(match_operand:GPR 3 "register_operand" "r")))]
- "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
- "czero.eqz\t%0,%3,%1"
-)
-
-(define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
- [(set (match_operand:GPR 0 "register_operand" "=r")
- (if_then_else:GPR (ne (match_operand:X 1 "register_operand" "r")
- (const_int 0))
- (match_operand:GPR 2 "register_operand" "r")
- (match_operand:GPR 3 "register_operand" "1")))]
- "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
- "czero.nez\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])"
+ {
+ if (TARGET_ZICOND)
+ return "czero.eqz\t%0,%3,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc\t%0,%3,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Combine creates this form in some cases (particularly the coremark
@@ -72,7 +86,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && TARGET_ZBS"
+ "TARGET_ZICOND_LIKE && TARGET_ZBS"
[(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
@@ -85,7 +99,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
[(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
new file mode 100644
index 000000000000..992f1425c54f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */
+/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
new file mode 100644
index 000000000000..04947de6156b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
+/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
new file mode 100644
index 000000000000..c2f0dc041cb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long xor1(long crc, long poly)
+{
+ if (crc & 1)
+ crc ^= poly;
+
+ return crc;
+}
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */
+/* { dg-final { scan-assembler-times "xor\t" 1 } } */
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-08-30 22:54 ` [RFC PATCH v2 0/1] " Tsukasa OI
2023-08-30 22:54 ` [RFC PATCH v2 1/1] " Tsukasa OI
@ 2023-09-05 12:10 ` Tsukasa OI
2023-09-05 12:10 ` [PATCH v3 1/1] " Tsukasa OI
2023-09-06 5:47 ` [PATCH v4 0/1] " Tsukasa OI
1 sibling, 2 replies; 12+ messages in thread
From: Tsukasa OI @ 2023-09-05 12:10 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
PATCH v1:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628786.html>
PATCH v2:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628872.html>
Changes: v1 -> v2
* Removed bogus opt2 pattern as pointed out in:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628867.html>
note that this is not in the ChangeLog expecting the patch above
applies first.
Changes: v2 -> v3
* Instead of removing opt2 pattern, fix opt2 pattern:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629137.html>
Tsukasa OI (1):
RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 51 +++++++++++++++----
.../xventanacondops-primitiveSemantics-rv32.c | 45 ++++++++++++++++
.../xventanacondops-primitiveSemantics.c | 48 +++++++++++++++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++
9 files changed, 162 insertions(+), 13 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
base-commit: 72b639760a891c406725854bfb08132c83f0761a
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-05 12:10 ` [PATCH v3 0/1] " Tsukasa OI
@ 2023-09-05 12:10 ` Tsukasa OI
2023-09-06 0:17 ` Jeff Law
2023-09-06 5:47 ` [PATCH v4 0/1] " Tsukasa OI
1 sibling, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2023-09-05 12:10 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.
And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).
* czero.eqz == vt.maskc
* czero.nez == vt.maskcn
This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support. With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.
The specification for the 'XVentanaCondOps' extension is based on:
<https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero.<eqz>.<GPR><X>): Ditto.
(*czero.eqz.<GPR><X>.opt1): Ditto.
(*czero.nez.<GPR><X>.opt2): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
modified from zicond-primitiveSemantics.c.
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
from zicond-xor-01.c.
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 51 +++++++++++++++----
.../xventanacondops-primitiveSemantics-rv32.c | 45 ++++++++++++++++
.../xventanacondops-primitiveSemantics.c | 48 +++++++++++++++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++
9 files changed, 162 insertions(+), 13 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index b6b5907e111b..a525f679683c 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -321,6 +321,12 @@ enum riscv_entity
#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
+#define MASK_XVENTANACONDOPS (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) != 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
+
/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8d8f7b4f16ed..eb10f4a3323f 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2745,7 +2745,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& outer_code == SET
&& ((GET_CODE (XEXP (x, 1)) == REG
&& XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
@@ -3842,7 +3842,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
cond, cons, alt)));
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& GET_MODE_CLASS (mode) == MODE_INT)
{
/* The comparison must be comparing WORD_MODE objects. We must
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 4041875e0e35..29ce75cf280c 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2580,7 +2580,7 @@
(if_then_else:GPR (match_operand 1 "comparison_operator")
(match_operand:GPR 2 "sfb_alu_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE"
{
if (riscv_expand_conditional_move (operands[0], operands[1],
operands[2], operands[3]))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index eca0dda4dd5c..3615f52ff0e0 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -257,6 +257,9 @@ int riscv_ztso_subext
TargetVariable
int riscv_xthead_subext
+TargetVariable
+int riscv_xventana_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 4619220ef8ac..8a690f160484 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -1,4 +1,5 @@
-;; Machine description for the RISC-V Zicond extension
+;; Machine description for the RISC-V Zicond extension and functionally-
+;; equivalent XVentanaCondOps vendor extension
;; Copyright (C) 2022-23 Free Software Foundation, Inc.
;; This file is part of GCC.
@@ -20,6 +21,8 @@
(define_code_iterator eq_or_ne [eq ne])
(define_code_attr eqz [(eq "nez") (ne "eqz")])
(define_code_attr nez [(eq "eqz") (ne "nez")])
+(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")])
+(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")])
;; Zicond
(define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
@@ -28,8 +31,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "r")
(const_int 0)))]
- "TARGET_ZICOND"
- "czero.<eqz>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<eqz>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.<eqz_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.<nez>.<GPR:mode><X:mode>"
@@ -38,8 +48,15 @@
(const_int 0))
(const_int 0)
(match_operand:GPR 2 "register_operand" "r")))]
- "TARGET_ZICOND"
- "czero.<nez>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<nez>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.<nez_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Special optimization under eq/ne in primitive semantics
@@ -49,8 +66,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "1")
(match_operand:GPR 3 "register_operand" "r")))]
- "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
- "czero.eqz\t%0,%3,%1"
+ "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])"
+ {
+ if (TARGET_ZICOND)
+ return "czero.eqz\t%0,%3,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc\t%0,%3,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
@@ -60,7 +84,14 @@
(match_operand:GPR 2 "register_operand" "r")
(match_operand:GPR 3 "register_operand" "1")))]
"TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
- "czero.nez\t%0,%2,%1"
+ {
+ if (TARGET_ZICOND)
+ return "czero.eqz\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Combine creates this form in some cases (particularly the coremark
@@ -72,7 +103,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && TARGET_ZBS"
+ "TARGET_ZICOND_LIKE && TARGET_ZBS"
[(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
@@ -85,7 +116,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
[(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
new file mode 100644
index 000000000000..992f1425c54f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
@@ -0,0 +1,45 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */
+/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
new file mode 100644
index 000000000000..04947de6156b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
+
+long primitiveSemantics_00(long a, long b) { return a == 0 ? 0 : b; }
+
+long primitiveSemantics_01(long a, long b) { return a != 0 ? 0 : b; }
+
+long primitiveSemantics_02(long a, long b) { return a == 0 ? b : 0; }
+
+long primitiveSemantics_03(long a, long b) { return a != 0 ? b : 0; }
+
+long primitiveSemantics_04(long a, long b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+long primitiveSemantics_05(long a, long b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_06(int a, int b) { return a == 0 ? 0 : b; }
+
+int primitiveSemantics_07(int a, int b) { return a != 0 ? 0 : b; }
+
+int primitiveSemantics_08(int a, int b) { return a == 0 ? b : 0; }
+
+int primitiveSemantics_09(int a, int b) { return a != 0 ? b : 0; }
+
+int primitiveSemantics_10(int a, int b) {
+ if (a)
+ b = 0;
+ return b;
+}
+
+int primitiveSemantics_11(int a, int b) {
+ if (!a)
+ b = 0;
+ return b;
+}
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
+/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
new file mode 100644
index 000000000000..c2f0dc041cb1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long xor1(long crc, long poly)
+{
+ if (crc & 1)
+ crc ^= poly;
+
+ return crc;
+}
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */
+/* { dg-final { scan-assembler-times "xor\t" 1 } } */
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-05 12:10 ` [PATCH v3 1/1] " Tsukasa OI
@ 2023-09-06 0:17 ` Jeff Law
2023-09-06 2:33 ` Tsukasa OI
0 siblings, 1 reply; 12+ messages in thread
From: Jeff Law @ 2023-09-06 0:17 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman, Jim Wilson
Cc: gcc-patches
On 9/5/23 06:10, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
> containing two instructions for conditional move and will be supported on
> their Veyron V1 CPU.
>
> And most notably (for historical reasons), 'XVentanaCondOps' and the
> standard 'Zicond' extension are functionally equivalent (only encodings and
> instruction names are different).
>
> * czero.eqz == vt.maskc
> * czero.nez == vt.maskcn
>
> This commit adds support for the 'XVentanaCondOps' extension by extending
> 'Zicond' extension support. With this, we can now reuse the optimization
> using the 'Zicond' extension for the 'XVentanaCondOps' extension.
>
> The specification for the 'XVentanaCondOps' extension is based on:
> <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
> Parse 'XVentanaCondOps' extension.
> * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
> (TARGET_XVENTANACONDOPS): Ditto.
> (TARGET_ZICOND_LIKE): New to represent targets with conditional
> moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
> * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
> with TARGET_ZICOND_LIKE.
> (riscv_expand_conditional_move): Ditto.
> * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
> TARGET_ZICOND_LIKE.
> * config/riscv/riscv.opt: Add new riscv_xventana_subext.
> * config/riscv/zicond.md: Modify description.
> (eqz_ventana): New to match corresponding czero instructions.
> (nez_ventana): Ditto.
> (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
> 'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
> (*czero.<eqz>.<GPR><X>): Ditto.
> (*czero.eqz.<GPR><X>.opt1): Ditto.
> (*czero.nez.<GPR><X>.opt2): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
> modified from zicond-primitiveSemantics.c.
> * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
> test to make sure that XVentanaCondOps instructions are disabled
> on RV32.
> * gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
> from zicond-xor-01.c.
> ---
> gcc/common/config/riscv/riscv-common.cc | 2 +
\
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 8d8f7b4f16ed..eb10f4a3323f 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2745,7 +2745,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
> *total = COSTS_N_INSNS (1);
> return true;
> }
> - else if (TARGET_ZICOND
> + else if (TARGET_ZICOND_LIKE
Internally we have this as:
(TARGET_ZICOND || TARGET_XVENTANACONDOPS)
I don't really care, so I'm happy to go with yours.
> +(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")])
> +(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")])
We did these as N/n which output n or nothing:
(define_code_attr n [(eq "n") (ne "")])
(define_code_attr N [(eq "") (ne "n")])
>
> ;; Zicond
> (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
> @@ -28,8 +31,15 @@
> (const_int 0))
> (match_operand:GPR 2 "register_operand" "r")
> (const_int 0)))]
> - "TARGET_ZICOND"
> - "czero.<eqz>\t%0,%2,%1"
> + "TARGET_ZICOND_LIKE"
> + {
> + if (TARGET_ZICOND)
> + return "czero.<eqz>\t%0,%2,%1";
> + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
> + return "vt.<eqz_ventana>\t%0,%2,%1";
> + else
> + gcc_unreachable ();
> + }
> )
And so the output template ends up like this:
> "* return TARGET_ZICOND ? \"czero.<eqz>\t%0,%2,%1\" : \"vt.maskc<n>\t%0,%2,%1\"; "
But again, I don't care enough about this to make it a big deal and I'm
happy to go with your approach.
> diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
> new file mode 100644
> index 000000000000..992f1425c54f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
So we're never going to have an rv32 variant. So I don't think we need
rv32 xventanacondops tests.
For the tests we keep, the right way to do them is with #includes.
ie start with this:
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
Then #include the zicond variant of the test
> +
> +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
> +/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
> +/* { dg-final { scan-assembler-not "beq" } } */
> +/* { dg-final { scan-assembler-not "bne" } } */
Then you have the assembly scan strings.
That way we don't duplicate the actual test code.
If you could fixup the tests, then I think this will be ready to integrate.
Thanks,
jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-06 0:17 ` Jeff Law
@ 2023-09-06 2:33 ` Tsukasa OI
2023-09-06 3:07 ` Jeff Law
0 siblings, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2023-09-06 2:33 UTC (permalink / raw)
To: Jeff Law; +Cc: GCC Patches
On 2023/09/06 9:17, Jeff Law wrote:
>
>
> On 9/5/23 06:10, Tsukasa OI wrote:
>> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>>
>> 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
>> containing two instructions for conditional move and will be supported on
>> their Veyron V1 CPU.
>>
>> And most notably (for historical reasons), 'XVentanaCondOps' and the
>> standard 'Zicond' extension are functionally equivalent (only
>> encodings and
>> instruction names are different).
>>
>> * czero.eqz == vt.maskc
>> * czero.nez == vt.maskcn
>>
>> This commit adds support for the 'XVentanaCondOps' extension by extending
>> 'Zicond' extension support. With this, we can now reuse the optimization
>> using the 'Zicond' extension for the 'XVentanaCondOps' extension.
>>
>> The specification for the 'XVentanaCondOps' extension is based on:
>> <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
>>
>> gcc/ChangeLog:
>>
>> * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
>> Parse 'XVentanaCondOps' extension.
>> * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
>> (TARGET_XVENTANACONDOPS): Ditto.
>> (TARGET_ZICOND_LIKE): New to represent targets with conditional
>> moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
>> * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
>> with TARGET_ZICOND_LIKE.
>> (riscv_expand_conditional_move): Ditto.
>> * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
>> TARGET_ZICOND_LIKE.
>> * config/riscv/riscv.opt: Add new riscv_xventana_subext.
>> * config/riscv/zicond.md: Modify description.
>> (eqz_ventana): New to match corresponding czero instructions.
>> (nez_ventana): Ditto.
>> (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
>> 'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
>> (*czero.<eqz>.<GPR><X>): Ditto.
>> (*czero.eqz.<GPR><X>.opt1): Ditto.
>> (*czero.nez.<GPR><X>.opt2): Ditto.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
>> modified from zicond-primitiveSemantics.c.
>> * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
>> test to make sure that XVentanaCondOps instructions are disabled
>> on RV32.
>> * gcc.target/riscv/xventanacondops-xor-01.c: New test, modified
>> from zicond-xor-01.c.
>> ---
>> gcc/common/config/riscv/riscv-common.cc | 2 +
> \
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 8d8f7b4f16ed..eb10f4a3323f 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -2745,7 +2745,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
>> outer_code, int opno ATTRIBUTE_UN
>> *total = COSTS_N_INSNS (1);
>> return true;
>> }
>> - else if (TARGET_ZICOND
>> + else if (TARGET_ZICOND_LIKE
> Internally we have this as:
>
> (TARGET_ZICOND || TARGET_XVENTANACONDOPS)
>
> I don't really care, so I'm happy to go with yours.
Because XVentanaCondOps instructions are only available on 64-bit target
(I wanted to prevent misuses because we don't reject XVentanaCondOps on
RV32), the target expression would be:
(a) (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
and I had three options to deal with it.
1. Use the plain expression (a)
2. Name the expression (a)
3. Enable TARGET_XVENTANACONDOPS only on 64-bit target
I think option 2 is the simplest yet understandable.
>
>
>> +(define_code_attr eqz_ventana [(eq "maskcn") (ne "maskc")])
>> +(define_code_attr nez_ventana [(eq "maskc") (ne "maskcn")])
> We did these as N/n which output n or nothing:
>
> (define_code_attr n [(eq "n") (ne "")])
> (define_code_attr N [(eq "") (ne "n")])
That's a great idea. I will stick to "eqz_ventana" and "nez_ventana"
but will change the contents to "n" and "".
>
>
>> ;; Zicond
>> (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
>> @@ -28,8 +31,15 @@
>> (const_int 0))
>> (match_operand:GPR 2 "register_operand"
>> "r")
>> (const_int 0)))]
>> - "TARGET_ZICOND"
>> - "czero.<eqz>\t%0,%2,%1"
>> + "TARGET_ZICOND_LIKE"
>> + {
>> + if (TARGET_ZICOND)
>> + return "czero.<eqz>\t%0,%2,%1";
>> + else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
>> + return "vt.<eqz_ventana>\t%0,%2,%1";
>> + else
>> + gcc_unreachable ();
>> + }
>> )
> And so the output template ends up like this:
>
>> "* return TARGET_ZICOND ? \"czero.<eqz>\t%0,%2,%1\" :
>> \"vt.maskc<n>\t%0,%2,%1\"; "
>
> But again, I don't care enough about this to make it a big deal and I'm
> happy to go with your approach.
>
>
>
>> diff --git
>> a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
>> new file mode 100644
>> index 000000000000..992f1425c54f
>> --- /dev/null
>> +++
>> b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
> So we're never going to have an rv32 variant. So I don't think we need
> rv32 xventanacondops tests.
>
> For the tests we keep, the right way to do them is with #includes.
>
> ie start with this:
>
>
>
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
>> +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
>
> Then #include the zicond variant of the test
>
>
>> +
>> +/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
>> +/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
>> +/* { dg-final { scan-assembler-not "beq" } } */
>> +/* { dg-final { scan-assembler-not "bne" } } */
> Then you have the assembly scan strings.
>
> That way we don't duplicate the actual test code.
>
> If you could fixup the tests, then I think this will be ready to integrate.
>
> Thanks,
> jeff
>
I'm happy to hear that because I had no confidence so whether we can use
#include to share common parts. I haven't tried yet but I believe we
have to #include only common parts (not including dg instructions
containing -march=..._zicond) so I will likely required to modify zicond
tests as well.
I'll submit PATCH v4 (not committing directly) as changes will be a bit
larger (and Jeff's words seem "near approval" even after fixing the
tests, not complete approval).
Thanks,
Tsukasa
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-06 2:33 ` Tsukasa OI
@ 2023-09-06 3:07 ` Jeff Law
2023-09-06 3:16 ` Palmer Dabbelt
0 siblings, 1 reply; 12+ messages in thread
From: Jeff Law @ 2023-09-06 3:07 UTC (permalink / raw)
To: Tsukasa OI; +Cc: GCC Patches
On 9/5/23 20:33, Tsukasa OI wrote:
>> Internally we have this as:
>>
>> (TARGET_ZICOND || TARGET_XVENTANACONDOPS)
>>
>> I don't really care, so I'm happy to go with yours.
>
> Because XVentanaCondOps instructions are only available on 64-bit target
> (I wanted to prevent misuses because we don't reject XVentanaCondOps on
> RV32), the target expression would be:
>
> (a) (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
>
> and I had three options to deal with it.
>
> 1. Use the plain expression (a)
> 2. Name the expression (a)
> 3. Enable TARGET_XVENTANACONDOPS only on 64-bit target
>
> I think option 2 is the simplest yet understandable.
Sure. It may also give us the option to roll in some of the thead code
at some point. Their conditional move support seems to line up pretty
well with zicond/xventanacondops too, though I haven't looked at it very
deeply yet.
>>
>
> I'm happy to hear that because I had no confidence so whether we can use
> #include to share common parts. I haven't tried yet but I believe we
> have to #include only common parts (not including dg instructions
> containing -march=..._zicond) so I will likely required to modify zicond
> tests as well.
You actually don't even have to break out the common parts. The dg-
directives in an included file aren't parsed by the dg framework.
>
> I'll submit PATCH v4 (not committing directly) as changes will be a bit
> larger (and Jeff's words seem "near approval" even after fixing the
> tests, not complete approval).
Sounds perfect. Given the bulk of the review work is already done, the
final review ack will be easy.
jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v3 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-06 3:07 ` Jeff Law
@ 2023-09-06 3:16 ` Palmer Dabbelt
0 siblings, 0 replies; 12+ messages in thread
From: Palmer Dabbelt @ 2023-09-06 3:16 UTC (permalink / raw)
To: gcc-patches; +Cc: research_trasio, gcc-patches
On Tue, 05 Sep 2023 20:07:16 PDT (-0700), gcc-patches@gcc.gnu.org wrote:
>
>
> On 9/5/23 20:33, Tsukasa OI wrote:
>
>> Internally we have this as:
>>>
>>> (TARGET_ZICOND || TARGET_XVENTANACONDOPS)
>>>
>>> I don't really care, so I'm happy to go with yours.
>
>> Because XVentanaCondOps instructions are only available on 64-bit target
>> (I wanted to prevent misuses because we don't reject XVentanaCondOps on
>> RV32), the target expression would be:
>>
>> (a) (TARGT_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
>>
>> and I had three options to deal with it.
>>
>> 1. Use the plain expression (a)
>> 2. Name te expression (a)
>> 3. Enable TARGET_XVENTANACONDOPS only on 64-bit target
>>
>> I think option 2 is the simplest yet understandable.
> Sure. It may also give us the option to roll in some of the thead code
> at some point. Their conditional move support seems to line up pretty
> well with zicond/xventanacondops too, though I haven't looked at it very
> deeply yet.
IIUC the T-Head stuff is actually a conditional move, so it's a little
different than the conditional move/zero extensions (which IIUC have
exactly the same semantics, just different encodings). Hopefully the
cmov fits in a bit easier, we shouldn't need to juggle the extra 0
input.
>> I'm happy to hear that because I had no confidence so whether we can use
>> #include to share common parts. I haven't tried yet but I believe we
>> have to #include only common parts (not including dg instructions
>> containing -march=..._zicond) so I will likely required to modify zicond
>> tests as well.
> You actually don't even have to break out the common parts. The dg-
> directives in an included file aren't parsed by the dg framework.
>
>
>>
>> I'll submit PATCH v4 (not committing directly) as changes will be a bit
>> larger (and Jeff's words seem "near approval" even after fixing the
>> tests, not complete approval).
> Sounds perfect. Given the bulk of the review work is already done, the
> final review ack will be easy.
>
> jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 0/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-05 12:10 ` [PATCH v3 0/1] " Tsukasa OI
2023-09-05 12:10 ` [PATCH v3 1/1] " Tsukasa OI
@ 2023-09-06 5:47 ` Tsukasa OI
2023-09-06 5:47 ` [PATCH v4 1/1] " Tsukasa OI
1 sibling, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2023-09-06 5:47 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
PATCH v1:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628786.html>
PATCH v2:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628872.html>
PATCH v3:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629332.html>
Changes: v1 -> v2
* Removed bogus opt2 pattern as pointed out in:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628867.html>
note that this is not in the ChangeLog expecting the patch above
applies first.
Changes: v2 -> v3
* Instead of removing opt2 pattern, fix opt2 pattern:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629137.html>
Changes: v3 -> v4
* Leave only specific condition on {eq,ne}z_ventana code_attr.
(eqz_ventana, nez_ventana): "maskcn" -> "n", "maskc" -> ""
(*czero.<eqz>.<GPR><X>) "vt.<eqz_ventana>" -> "vt.maskc<eqz_ventana>"
(*czero.<nez>.<GPR><X>) "vt.<nez_ventana>" -> "vt.maskc<nez_ventana>"
* Testsuite:
Reuse "zicond-*.c" (#include from "xventanacondops-*.c")
* Minor Comment: ";; Zicond" -> ";; Zicond / XVentanaCondOps"
* Rebase against commit e87212ead5e9 ("RISC-V: zicond: Fix opt2 pattern")
On 2023/09/06 12:07, Jeff Law wrote:
> You actually don't even have to break out the common parts. The dg-
> directives in an included file aren't parsed by the dg framework.
Wow, that was right. It can be sometimes confusing but very useful
in this case. Thanks for the info!
Sincerely,
Tsukasa
Tsukasa OI (1):
RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 53 +++++++++++++++----
.../xventanacondops-primitiveSemantics-rv32.c | 8 +++
.../xventanacondops-primitiveSemantics.c | 10 ++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 8 +++
9 files changed, 82 insertions(+), 14 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
base-commit: c1597e7fb9f9ecb9d7c33b5afa48031f284375de
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v4 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-06 5:47 ` [PATCH v4 0/1] " Tsukasa OI
@ 2023-09-06 5:47 ` Tsukasa OI
2023-09-06 14:04 ` Jeff Law
0 siblings, 1 reply; 12+ messages in thread
From: Tsukasa OI @ 2023-09-06 5:47 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman,
Jim Wilson, Jeff Law
Cc: gcc-patches
From: Tsukasa OI <research_trasio@irq.a4lg.com>
'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
containing two instructions for conditional move and will be supported on
their Veyron V1 CPU.
And most notably (for historical reasons), 'XVentanaCondOps' and the
standard 'Zicond' extension are functionally equivalent (only encodings and
instruction names are different).
* czero.eqz == vt.maskc
* czero.nez == vt.maskcn
This commit adds support for the 'XVentanaCondOps' extension by extending
'Zicond' extension support. With this, we can now reuse the optimization
using the 'Zicond' extension for the 'XVentanaCondOps' extension.
The specification for the 'XVentanaCondOps' extension is based on:
<https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
Parse 'XVentanaCondOps' extension.
* config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
(TARGET_XVENTANACONDOPS): Ditto.
(TARGET_ZICOND_LIKE): New to represent targets with conditional
moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
* config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
with TARGET_ZICOND_LIKE.
(riscv_expand_conditional_move): Ditto.
* config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
TARGET_ZICOND_LIKE.
* config/riscv/riscv.opt: Add new riscv_xventana_subext.
* config/riscv/zicond.md: Modify description.
(eqz_ventana): New to match corresponding czero instructions.
(nez_ventana): Ditto.
(*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
(*czero.<eqz>.<GPR><X>): Ditto.
(*czero.eqz.<GPR><X>.opt1): Ditto.
(*czero.nez.<GPR><X>.opt2): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
* gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
test to make sure that XVentanaCondOps instructions are disabled
on RV32.
* gcc.target/riscv/xventanacondops-xor-01.c: New test,
---
gcc/common/config/riscv/riscv-common.cc | 2 +
gcc/config/riscv/riscv-opts.h | 6 +++
gcc/config/riscv/riscv.cc | 4 +-
gcc/config/riscv/riscv.md | 2 +-
gcc/config/riscv/riscv.opt | 3 ++
gcc/config/riscv/zicond.md | 53 +++++++++++++++----
.../xventanacondops-primitiveSemantics-rv32.c | 8 +++
.../xventanacondops-primitiveSemantics.c | 10 ++++
.../gcc.target/riscv/xventanacondops-xor-01.c | 8 +++
9 files changed, 82 insertions(+), 14 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index f142212f2edc..9a0a68fe5db3 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1493,6 +1493,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
{"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
{"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
+ {"xventanacondops", &gcc_options::x_riscv_xventana_subext, MASK_XVENTANACONDOPS},
+
{NULL, NULL, 0}
};
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index b6b5907e111b..a525f679683c 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -321,6 +321,12 @@ enum riscv_entity
#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
+#define MASK_XVENTANACONDOPS (1 << 0)
+
+#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS) != 0)
+
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
+
/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS \
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 475fb2841427..a6e58e4f1159 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2744,7 +2744,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (1);
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& outer_code == SET
&& ((GET_CODE (XEXP (x, 1)) == REG
&& XEXP (x, 2) == CONST0_RTX (GET_MODE (XEXP (x, 1))))
@@ -3841,7 +3841,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx cons, rtx alt)
cond, cons, alt)));
return true;
}
- else if (TARGET_ZICOND
+ else if (TARGET_ZICOND_LIKE
&& GET_MODE_CLASS (mode) == MODE_INT)
{
/* The comparison must be comparing WORD_MODE objects. We must
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d80b6938f84b..03833be7129b 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2608,7 +2608,7 @@
(if_then_else:GPR (match_operand 1 "comparison_operator")
(match_operand:GPR 2 "sfb_alu_operand")
(match_operand:GPR 3 "sfb_alu_operand")))]
- "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND"
+ "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV || TARGET_ZICOND_LIKE"
{
if (riscv_expand_conditional_move (operands[0], operands[1],
operands[2], operands[3]))
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index eca0dda4dd5c..3615f52ff0e0 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -257,6 +257,9 @@ int riscv_ztso_subext
TargetVariable
int riscv_xthead_subext
+TargetVariable
+int riscv_xventana_subext
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index c28bee5d5709..6627be3fa585 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -1,4 +1,5 @@
-;; Machine description for the RISC-V Zicond extension
+;; Machine description for the RISC-V Zicond extension and functionally-
+;; equivalent XVentanaCondOps vendor extension
;; Copyright (C) 2022-23 Free Software Foundation, Inc.
;; This file is part of GCC.
@@ -20,16 +21,25 @@
(define_code_iterator eq_or_ne [eq ne])
(define_code_attr eqz [(eq "nez") (ne "eqz")])
(define_code_attr nez [(eq "eqz") (ne "nez")])
+(define_code_attr eqz_ventana [(eq "n") (ne "")])
+(define_code_attr nez_ventana [(eq "") (ne "n")])
-;; Zicond
+;; Zicond / XVentanaCondOps
(define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
(if_then_else:GPR (eq_or_ne (match_operand:X 1 "register_operand" "r")
(const_int 0))
(match_operand:GPR 2 "register_operand" "r")
(const_int 0)))]
- "TARGET_ZICOND"
- "czero.<eqz>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<eqz>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc<eqz_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.<nez>.<GPR:mode><X:mode>"
@@ -38,8 +48,15 @@
(const_int 0))
(const_int 0)
(match_operand:GPR 2 "register_operand" "r")))]
- "TARGET_ZICOND"
- "czero.<nez>\t%0,%2,%1"
+ "TARGET_ZICOND_LIKE"
+ {
+ if (TARGET_ZICOND)
+ return "czero.<nez>\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc<nez_ventana>\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Special optimization under eq/ne in primitive semantics
@@ -49,8 +66,15 @@
(const_int 0))
(match_operand:GPR 2 "register_operand" "1")
(match_operand:GPR 3 "register_operand" "r")))]
- "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
- "czero.eqz\t%0,%3,%1"
+ "TARGET_ZICOND_LIKE && rtx_equal_p (operands[1], operands[2])"
+ {
+ if (TARGET_ZICOND)
+ return "czero.eqz\t%0,%3,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc\t%0,%3,%1";
+ else
+ gcc_unreachable ();
+ }
)
(define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
@@ -60,7 +84,14 @@
(match_operand:GPR 2 "register_operand" "r")
(match_operand:GPR 3 "register_operand" "1")))]
"TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
- "czero.eqz\t%0,%2,%1"
+ {
+ if (TARGET_ZICOND)
+ return "czero.eqz\t%0,%2,%1";
+ else if (TARGET_XVENTANACONDOPS && TARGET_64BIT)
+ return "vt.maskc\t%0,%2,%1";
+ else
+ gcc_unreachable ();
+ }
)
;; Combine creates this form in some cases (particularly the coremark
@@ -72,7 +103,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && TARGET_ZBS"
+ "TARGET_ZICOND_LIKE && TARGET_ZBS"
[(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
@@ -85,7 +116,7 @@
(match_operand 2 "immediate_operand"))
(match_operand:X 3 "register_operand")))
(clobber (match_operand:X 4 "register_operand"))]
- "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+ "TARGET_ZICOND_LIKE && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
[(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
(set (match_dup 0) (if_then_else:X (eq:X (match_dup 4) (const_int 0))
(const_int 0)
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
new file mode 100644
index 000000000000..862ad309b52c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xventanacondops -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
+
+#include "zicond-primitiveSemantics.c"
+
+/* { dg-final { scan-assembler-not "vt\\.maskc\t" } } */
+/* { dg-final { scan-assembler-not "vt\\.maskcn\t" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
new file mode 100644
index 000000000000..644ca12d6470
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-primitiveSemantics.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Og"} } */
+
+#include "zicond-primitiveSemantics.c"
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 6 } } */
+/* { dg-final { scan-assembler-times "vt\\.maskcn\t" 6 } } */
+/* { dg-final { scan-assembler-not "beq" } } */
+/* { dg-final { scan-assembler-not "bne" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
new file mode 100644
index 000000000000..634eff84f89d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+#include "zicond-xor-01.c"
+
+/* { dg-final { scan-assembler-times "vt\\.maskc\t" 1 } } */
+/* { dg-final { scan-assembler-times "xor\t" 1 } } */
--
2.42.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v4 1/1] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support
2023-09-06 5:47 ` [PATCH v4 1/1] " Tsukasa OI
@ 2023-09-06 14:04 ` Jeff Law
0 siblings, 0 replies; 12+ messages in thread
From: Jeff Law @ 2023-09-06 14:04 UTC (permalink / raw)
To: Tsukasa OI, Kito Cheng, Palmer Dabbelt, Andrew Waterman, Jim Wilson
Cc: gcc-patches
On 9/5/23 23:47, Tsukasa OI wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> 'XVentanaCondOps' is a vendor extension from Ventana Micro Systems
> containing two instructions for conditional move and will be supported on
> their Veyron V1 CPU.
>
> And most notably (for historical reasons), 'XVentanaCondOps' and the
> standard 'Zicond' extension are functionally equivalent (only encodings and
> instruction names are different).
>
> * czero.eqz == vt.maskc
> * czero.nez == vt.maskcn
>
> This commit adds support for the 'XVentanaCondOps' extension by extending
> 'Zicond' extension support. With this, we can now reuse the optimization
> using the 'Zicond' extension for the 'XVentanaCondOps' extension.
>
> The specification for the 'XVentanaCondOps' extension is based on:
> <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_ext_flag_table):
> Parse 'XVentanaCondOps' extension.
> * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): New.
> (TARGET_XVENTANACONDOPS): Ditto.
> (TARGET_ZICOND_LIKE): New to represent targets with conditional
> moves like 'Zicond'. It includes RV64 + 'XVentanaCondOps'.
> * config/riscv/riscv.cc (riscv_rtx_costs): Replace TARGET_ZICOND
> with TARGET_ZICOND_LIKE.
> (riscv_expand_conditional_move): Ditto.
> * config/riscv/riscv.md (mov<mode>cc): Replace TARGET_ZICOND with
> TARGET_ZICOND_LIKE.
> * config/riscv/riscv.opt: Add new riscv_xventana_subext.
> * config/riscv/zicond.md: Modify description.
> (eqz_ventana): New to match corresponding czero instructions.
> (nez_ventana): Ditto.
> (*czero.<eqz>.<GPR><X>): Emit a 'XVentanaCondOps' instruction if
> 'Zicond' is not available but 'XVentanaCondOps' + RV64 is.
> (*czero.<eqz>.<GPR><X>): Ditto.
> (*czero.eqz.<GPR><X>.opt1): Ditto.
> (*czero.nez.<GPR><X>.opt2): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/xventanacondops-primitiveSemantics.c: New test,
> * gcc.target/riscv/xventanacondops-primitiveSemantics-rv32.c: New
> test to make sure that XVentanaCondOps instructions are disabled
> on RV32.
> * gcc.target/riscv/xventanacondops-xor-01.c: New test,
OK. Thanks for taking care of this. I guess Raphael and I should get
more active on pushing the rest of the veyron-v1 bits upstream :-)
Jeff
^ permalink raw reply [flat|nested] 12+ messages in thread
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2023-08-30 6:44 [RFC PATCH] RISC-V: Add support for 'XVentanaCondOps' reusing 'Zicond' support Tsukasa OI
2023-08-30 22:54 ` [RFC PATCH v2 0/1] " Tsukasa OI
2023-08-30 22:54 ` [RFC PATCH v2 1/1] " Tsukasa OI
2023-09-05 12:10 ` [PATCH v3 0/1] " Tsukasa OI
2023-09-05 12:10 ` [PATCH v3 1/1] " Tsukasa OI
2023-09-06 0:17 ` Jeff Law
2023-09-06 2:33 ` Tsukasa OI
2023-09-06 3:07 ` Jeff Law
2023-09-06 3:16 ` Palmer Dabbelt
2023-09-06 5:47 ` [PATCH v4 0/1] " Tsukasa OI
2023-09-06 5:47 ` [PATCH v4 1/1] " Tsukasa OI
2023-09-06 14:04 ` Jeff Law
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