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From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
	Kito Cheng <kito.cheng@gmail.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Andrew Waterman <andrew@sifive.com>,
	Jim Wilson <jim.wilson.gcc@gmail.com>,
	Jeff Law <jeffreyalaw@gmail.com>
Cc: gcc-patches@gcc.gnu.org
Subject: [PATCH 0/4] RISC-V: Fix 'Zicbop'-related bugs (fix ICE and remove broken built-in)
Date: Mon, 23 Oct 2023 07:22:51 +0000	[thread overview]
Message-ID: <cover.1698045769.git.research_trasio@irq.a4lg.com> (raw)

Hello,

As I explained earlier:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626916.html>,
the builtin function for RISC-V "__builtin_riscv_zicbop_cbo_prefetchi" is
completely broken and should be removed.

Also, I noted that:
<https://gcc.gnu.org/pipermail/gcc-patches/2023-September/631164.html>
__builtin_prefetch built-in function with the first argument NULL or (not
all but) some fixed addresses (like ((void*)0x20)) can cause an ICE.


Instead of making not broken prefetch built-in functions, this patch set
focuses on fixing those major bugs and intended for fast approval to make
it to GCC 14
(except renaming "prefetch" availabilities for built-in functions).


Thanks,
Tsukasa




Tsukasa OI (4):
  RISC-V: Recategorize "prefetch" availabilities
  RISC-V: Remove broken __builtin_riscv_zicbop_cbo_prefetchi
  RISC-V: Add not broken RW prefetch RTL instructions without offsets
  RISC-V: Fix ICE by expansion and register coercion

 gcc/config/riscv/riscv-builtins.cc            |  4 +-
 gcc/config/riscv/riscv-cmo.def                |  4 --
 gcc/config/riscv/riscv.md                     | 56 +++++++++++++------
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c |  6 --
 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c |  8 +--
 .../riscv/cmo-zicbop-by-common-ice-1.c        | 13 +++++
 .../riscv/cmo-zicbop-by-common-ice-2.c        |  7 +++
 7 files changed, 61 insertions(+), 37 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-by-common-ice-2.c


base-commit: c2d41cdfeadb82d921b01c0e104d83f47e2262a2
-- 
2.42.0


             reply	other threads:[~2023-10-23  7:23 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23  7:22 Tsukasa OI [this message]
2023-10-23  7:22 ` [PATCH 1/4] RISC-V: Recategorize "prefetch" availabilities Tsukasa OI
2023-10-30 21:57   ` Jeff Law
2023-10-31  1:17     ` Kito Cheng
2023-10-23  7:22 ` [PATCH 2/4] RISC-V: Remove broken __builtin_riscv_zicbop_cbo_prefetchi Tsukasa OI
2023-10-23  7:22 ` [PATCH 3/4] RISC-V: Add not broken RW prefetch RTL instructions without offsets Tsukasa OI
2023-10-23  7:22 ` [PATCH 4/4] RISC-V: Fix ICE by expansion and register coercion Tsukasa OI

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