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* [RFC] RISC-V: Handle new types in scheduling descriptions
@ 2023-10-09 21:02 Edwin Lu
  2023-10-10 17:11 ` Jeff Law
  0 siblings, 1 reply; 4+ messages in thread
From: Edwin Lu @ 2023-10-09 21:02 UTC (permalink / raw)
  To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu

Now that every insn is guaranteed a type, we want to ensure the types are 
handled by the existing scheduling descriptions. 

There are 2 approaches I see:
1. Create a new pipeline intended to eventually abort (sifive-7.md) 
2. Add the types to an existing pipeline (generic.md)

Which approach do we want to go with? If there is a different approach we
want to take instead, please let me know as well.

Additionally, should types associated with specific extensions 
(vector, crypto, etc) have specific pipelines dedicated to them? 

	* config/riscv/generic.md: update pipeline
	* config/riscv/sifive-7.md (sifive_7): update pipeline
	(sifive_7_other):

Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
 gcc/config/riscv/generic.md  | 3 ++-
 gcc/config/riscv/sifive-7.md | 7 +++++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/generic.md b/gcc/config/riscv/generic.md
index 57d3c3b4adc..338d2e85b77 100644
--- a/gcc/config/riscv/generic.md
+++ b/gcc/config/riscv/generic.md
@@ -27,7 +27,8 @@ (define_cpu_unit "fdivsqrt" "pipe0")
 
 (define_insn_reservation "generic_alu" 1
   (and (eq_attr "tune" "generic")
-       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop"))
+       (eq_attr "type" "unknown,const,arith,shift,slt,multi,auipc,nop,
+	  logical,move,bitmanip,min,max,minu,maxu,clz,ctz,cpop,trap,cbo"))
   "alu")
 
 (define_insn_reservation "generic_load" 3
diff --git a/gcc/config/riscv/sifive-7.md b/gcc/config/riscv/sifive-7.md
index 526278e46d4..e76d82614d6 100644
--- a/gcc/config/riscv/sifive-7.md
+++ b/gcc/config/riscv/sifive-7.md
@@ -12,6 +12,8 @@ (define_cpu_unit "sifive_7_B" "sifive_7")
 (define_cpu_unit "sifive_7_idiv" "sifive_7")
 (define_cpu_unit "sifive_7_fpu" "sifive_7")
 
+(define_cpu_unit "sifive_7_abort" "sifive_7")
+
 (define_insn_reservation "sifive_7_load" 3
   (and (eq_attr "tune" "sifive_7")
        (eq_attr "type" "load"))
@@ -106,6 +108,11 @@ (define_insn_reservation "sifive_7_f2i" 3
        (eq_attr "type" "mfc"))
   "sifive_7_A")
 
+(define_insn_reservation "sifive_7_other" 3
+  (and (eq_attr "tune" "sifive_7")
+       (eq_attr "type" "trap,cbo"))
+  "sifive_7_abort")
+
 (define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i,sifive_7_sfb_alu"
   "sifive_7_alu,sifive_7_branch")
 
-- 
2.34.1


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-10-10 21:18 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2023-10-09 21:02 [RFC] RISC-V: Handle new types in scheduling descriptions Edwin Lu
2023-10-10 17:11 ` Jeff Law
2023-10-10 21:18   ` Edwin Lu
2023-10-10 21:18     ` Edwin Lu

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