From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 117316 invoked by alias); 24 Jun 2019 08:10:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 117308 invoked by uid 89); 24 Jun 2019 08:10:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-5.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:1542, clarification X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 24 Jun 2019 08:10:07 +0000 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x5O89sOo062446 for ; Mon, 24 Jun 2019 04:10:05 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0b-001b2d01.pphosted.com with ESMTP id 2taqw8exqk-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 24 Jun 2019 04:09:59 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 24 Jun 2019 09:08:29 +0100 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp07.uk.ibm.com (192.168.101.137) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 24 Jun 2019 09:08:27 +0100 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x5O88P4w20643888 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 24 Jun 2019 08:08:25 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B44C2A4069; Mon, 24 Jun 2019 08:08:25 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 464B0A4040; Mon, 24 Jun 2019 08:08:24 +0000 (GMT) Received: from kewenlins-mbp.cn.ibm.com (unknown [9.200.147.215]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 24 Jun 2019 08:08:23 +0000 (GMT) Subject: Re: [PATCH] [RS6000] Change maddld match_operand from DI to GPR To: Segher Boessenkool Cc: Li Jia He , gcc-patches@gcc.gnu.org, wschmidt@linux.ibm.com References: <1561356005-71785-1-git-send-email-helijia@linux.ibm.com> <554458e6-9519-e2cb-9747-b424bb275534@linux.ibm.com> <20190624071945.GB7313@gate.crashing.org> <20190624080218.GD7313@gate.crashing.org> From: "Kewen.Lin" Date: Mon, 24 Jun 2019 08:10:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.14; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: <20190624080218.GD7313@gate.crashing.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit x-cbid: 19062408-0028-0000-0000-0000037D00BC X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19062408-0029-0000-0000-0000243D1CBB Message-Id: X-IsSubscribed: yes X-SW-Source: 2019-06/txt/msg01421.txt.bz2 Hi Segher, on 2019/6/24 下午4:02, Segher Boessenkool wrote: > Hi Kewen, > > On Mon, Jun 24, 2019 at 03:43:26PM +0800, Kewen.Lin wrote: >> on 2019/6/24 下午3:19, Segher Boessenkool wrote: >>> Newer ISAs require 64-bit to be implemented. There are no optional >>> 64-bit categories anymore. Since this instruction is enabled for P9 >>> (ISA 3.0) only (that's the TARGET_MODULO), it's fine. >>> >>> What you are saying is quite true for older CPUs/ISAs though: there you >>> have to make sure you are targetting a CPU that supports the 64-bit >>> categories, before using any 64-bit insns. >>> >>> But those days are gone :-) >> >> Good to know that, thanks a lot for the information! It's fine then. >> >> It sounds like we can have a clean up for some others like >> TARGET_EXTSWSLI. :) > > Yes, but be careful there! The insn patterns for this use DImode, which > does not mean the same thing without -mpowerpc64 (it's a register pair > then, not what you want). > > And it doesn't make much sense to allow this for SImode as well (using > GPR, perhaps), because the insn just is a shift left for SImode, and we > already have shift left instructions. > > So we might want to just directly say "TARGET_MODULO && TARGET_POWERPC64" > in those patterns (TARGET_MODULO is a funny way of saying "p9 or later"). > Thanks for further clarification! Yes, I agree with you. I just noticed that extswsli isn't like maddld and not suitable for SImode. Thanks, Kewen > > Segher >