Index: ChangeLog
===================================================================
--- ChangeLog	(revision 266893)
+++ ChangeLog	(working copy)
@@ -1,3 +1,9 @@
+2018-12-07  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/88349
+	* ira-costs.c (record_operand_costs): Check bigger reg class on
+	NO_REGS.
+
 2018-12-07  Richard Sandiford  <richard.sandiford@arm.com>
 
 	* config/aarch64/aarch64-sve.md (*mul<mode>3, *v<optab><mode>3):
Index: ira-costs.c
===================================================================
--- ira-costs.c	(revision 266862)
+++ ira-costs.c	(working copy)
@@ -1327,8 +1327,9 @@ record_operand_costs (rtx_insn *insn, en
 	     fit the the hard reg class (e.g. DImode for AREG on
 	     i386).  Check this and use a bigger class to get the
 	     right cost.  */
-	  if (! ira_hard_reg_in_set_p (other_regno, mode,
-				       reg_class_contents[hard_reg_class]))
+	  if (bigger_hard_reg_class != NO_REGS
+	      && ! ira_hard_reg_in_set_p (other_regno, mode,
+					  reg_class_contents[hard_reg_class]))
 	    hard_reg_class = bigger_hard_reg_class;
 	  i = regno == (int) REGNO (src) ? 1 : 0;
 	  for (k = cost_classes_ptr->num - 1; k >= 0; k--)
Index: testsuite/ChangeLog
===================================================================
--- testsuite/ChangeLog	(revision 266893)
+++ testsuite/ChangeLog	(working copy)
@@ -1,3 +1,8 @@
+2018-12-07  Vladimir Makarov  <vmakarov@redhat.com>
+
+	PR rtl-optimization/88349
+	* gcc.target/mips/pr88349.c: New.
+
 2018-12-07  Jakub Jelinek  <jakub@redhat.com>
 
 	PR c++/86669
Index: testsuite/gcc.target/mips/pr88349.c
===================================================================
--- testsuite/gcc.target/mips/pr88349.c	(nonexistent)
+++ testsuite/gcc.target/mips/pr88349.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-mel -mabi=32 -march=mips64r2 -fexpensive-optimizations" } */
+/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
+
+typedef int DI __attribute__((mode(DI)));
+typedef int SI __attribute__((mode(SI)));
+
+__attribute__((mips16)) SI
+f (SI x, SI y)
+{
+  return ((DI) x * y) >> 32;
+}
+
+/* { dg-final { scan-assembler-not "\tsw\t" } } */