[PATCH] [PR99581] Define relaxed memory and use it for aarch64

[PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

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The following patch solves P1 PR99581

     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581

The patch was successfully tested and bootstrapped on x86-64, ppc64le, 
aarch64.

Is it ok for the trunk?



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commit 20a38c39e57fe4d8a72391184e3b67129f0bf88c
Author: Vladimir N. Makarov <vmakarov@redhat.com>
Date:   Fri Mar 19 10:11:57 2021 -0400

    [PR99581] Define relaxed memory and use it for aarch64
    
    aarch64 needs to skip memory address validation for LD1R insns.  Skipping
    the address validation may result in LRA crash for some targets when usual
    memory constraint is used.  This patch introduces define_relaxed_memory_constraint,
    skipping address validation for it, and defining relaxed memory for
    aarch64 LD1r insn memory operand.
    
    gcc/ChangeLog:
    
            PR target/99581
            * config/aarch64/constraints.md (UtQ): Use
            define_relaxed_memory_constraint for it.
            * doc/md.text (define_relaxed_memory_constraint): Describe it.
            * genoutput.c (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * gepreds.c (constraint_data): Add bitfield is_relaxed_memory.
            (have_relaxed_memory_constraints): New static var.
            (relaxed_memory_start, relaxed_memory_end): Ditto.
            (add_constraint): Add arg is_relaxed_memory.  Check name for
            relaxed memory.  Set up is_relaxed_memory in constraint_data and
            have_relaxed_memory_constraints.  Adjust calls.
            (choose_enum_order): Process relaxed memory.
            (write_tm_preds_h): Ditto.
            (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * gensupport.c (process_rtx): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * ira-costs.c (record_reg_classes): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * ira-lives.c (single_reg_class): Use
            insn_extra_relaxed_memory_constraint.
            * ira.c (ira_setup_alts): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * lra-constraints.c (valid_address_p): Use
            insn_extra_relaxed_memory_constraint instead of other memory
            constraints.
            (process_alt_operands): Process CT_RELAXED_MEMORY.
            (curr_insn_transform): Use insn_extra_relaxed_memory_constraint.
            * recog.c (asm_operand_ok, preprocess_constraints): Process
            CT_RELAXED_MEMORY.
            * reload.c (find_reloads): Ditto.
            * rtl.def (DEFINE_RELAXED_MEMORY_CONSTRAINT): New.
            * gcc/stmt.c (parse_input_constraint): Use
            insn_extra_relaxed_memory_constraint.
    
    gcc/testsuite/ChangeLog:
    
            PR target/99581
            * gcc.target/powerpc/pr99581.c: New.

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 09c2b7283e3..f08eea8bcae 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -330,7 +330,7 @@
        (match_test "aarch64_legitimate_address_p (V2DImode,
 						  XEXP (op, 0), 1)")))
 
-(define_memory_constraint "UtQ"
+(define_relaxed_memory_constraint "UtQ"
   "@internal
    An address valid for SVE LD1RQs."
   (and (match_code "mem")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index e3686dbfe61..90dd0401fa0 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -4567,6 +4567,17 @@ The syntax and semantics are otherwise identical to
 @code{define_constraint}.
 @end deffn
 
+@deffn {MD Expression} define_relaxed_memory_constraint name docstring exp
+Usually memory address in @code{reload} pass is checked to be a legitimate
+one besides checking the memory itself to satisfy the instruction
+constraint.  Sometimes you need to avoid legitimate address check for
+memory and use only check for memory to satisfy the constraint.  Use
+this expression to describe operands for such cases.
+
+The syntax and semantics are otherwise identical to
+@code{define_constraint}.
+@end deffn
+
 @deffn {MD Expression} define_address_constraint name docstring exp
 Use this expression for constraints that match a subset of all address
 operands: that is, @code{reload} can make the constraint match by
diff --git a/gcc/genoutput.c b/gcc/genoutput.c
index b88e13b90b6..25af4375d9c 100644
--- a/gcc/genoutput.c
+++ b/gcc/genoutput.c
@@ -1024,6 +1024,7 @@ main (int argc, const char **argv)
       case DEFINE_ADDRESS_CONSTRAINT:
       case DEFINE_MEMORY_CONSTRAINT:
       case DEFINE_SPECIAL_MEMORY_CONSTRAINT:
+      case DEFINE_RELAXED_MEMORY_CONSTRAINT:
 	note_constraint (&info);
 	break;
 
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 8499a2a2383..35b6ef344ab 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -660,9 +660,9 @@ write_one_predicate_function (struct pred_data *p)
 /* Constraints fall into two categories: register constraints
    (define_register_constraint), and others (define_constraint,
    define_memory_constraint, define_special_memory_constraint,
-   define_address_constraint).  We work out automatically which of the
-   various old-style macros they correspond to, and produce
-   appropriate code.  They all go in the same hash table so we can
+   define_relaxed_memory_constraint, define_address_constraint).  We work out
+   automatically which of the various old-style macros they correspond to, and
+   produce appropriate code.  They all go in the same hash table so we can
    verify that there are no duplicate names.  */
 
 /* All data from one constraint definition.  */
@@ -683,6 +683,7 @@ public:
   unsigned int is_extra		: 1;
   unsigned int is_memory	: 1;
   unsigned int is_special_memory: 1;
+  unsigned int is_relaxed_memory: 1;
   unsigned int is_address	: 1;
   unsigned int maybe_allows_reg : 1;
   unsigned int maybe_allows_mem : 1;
@@ -721,6 +722,7 @@ static unsigned int constraint_max_namelen;
 static bool have_register_constraints;
 static bool have_memory_constraints;
 static bool have_special_memory_constraints;
+static bool have_relaxed_memory_constraints;
 static bool have_address_constraints;
 static bool have_extra_constraints;
 static bool have_const_int_constraints;
@@ -732,6 +734,7 @@ static unsigned int satisfied_start;
 static unsigned int const_int_start, const_int_end;
 static unsigned int memory_start, memory_end;
 static unsigned int special_memory_start, special_memory_end;
+static unsigned int relaxed_memory_start, relaxed_memory_end;
 static unsigned int address_start, address_end;
 static unsigned int maybe_allows_none_start, maybe_allows_none_end;
 static unsigned int maybe_allows_reg_start, maybe_allows_reg_end;
@@ -756,15 +759,15 @@ mangle (const char *name)
   return XOBFINISH (rtl_obstack, const char *);
 }
 
-/* Add one constraint, of any sort, to the tables.  NAME is its name;
-   REGCLASS is the register class, if any; EXP is the expression to
-   test, if any; IS_MEMORY, IS_SPECIAL_MEMORY and IS_ADDRESS indicate
-   memory, special memory, and address constraints, respectively; LOC
-   is the .md file location.
+/* Add one constraint, of any sort, to the tables.  NAME is its name; REGCLASS
+   is the register class, if any; EXP is the expression to test, if any;
+   IS_MEMORY, IS_SPECIAL_MEMORY, IS_RELAXED_MEMORY and IS_ADDRESS indicate
+   memory, special memory, and address constraints, respectively; LOC is the .md
+   file location.
 
    Not all combinations of arguments are valid; most importantly,
    REGCLASS is mutually exclusive with EXP, and
-   IS_MEMORY/IS_SPECIAL_MEMORY/IS_ADDRESS are only meaningful for
+   IS_MEMORY/IS_SPECIAL_MEMORY/IS_RELAXED_MEMORY/IS_ADDRESS are only meaningful for
    constraints with EXP.
 
    This function enforces all syntactic and semantic rules about what
@@ -773,7 +776,7 @@ mangle (const char *name)
 static void
 add_constraint (const char *name, const char *regclass,
 		rtx exp, bool is_memory, bool is_special_memory,
-		bool is_address, file_location loc)
+		bool is_relaxed_memory, bool is_address, file_location loc)
 {
   class constraint_data *c, **iter, **slot;
   const char *p;
@@ -895,6 +898,17 @@ add_constraint (const char *name, const char *regclass,
 		      name, name[0]);
 	  return;
 	}
+      else if (is_relaxed_memory)
+	{
+	  if (name[1] == '\0')
+	    error_at (loc, "constraint letter '%c' cannot be a "
+		      "relaxed memory constraint", name[0]);
+	  else
+	    error_at (loc, "constraint name '%s' begins with '%c', "
+		      "and therefore cannot be a relaxed memory constraint",
+		      name, name[0]);
+	  return;
+	}
       else if (is_address)
 	{
 	  if (name[1] == '\0')
@@ -922,6 +936,7 @@ add_constraint (const char *name, const char *regclass,
   c->is_extra = !(regclass || is_const_int || is_const_dbl);
   c->is_memory = is_memory;
   c->is_special_memory = is_special_memory;
+  c->is_relaxed_memory = is_relaxed_memory;
   c->is_address = is_address;
   c->maybe_allows_reg = true;
   c->maybe_allows_mem = true;
@@ -949,19 +964,21 @@ add_constraint (const char *name, const char *regclass,
   have_extra_constraints |= c->is_extra;
   have_memory_constraints |= c->is_memory;
   have_special_memory_constraints |= c->is_special_memory;
+  have_relaxed_memory_constraints |= c->is_relaxed_memory;
   have_address_constraints |= c->is_address;
   num_constraints += 1;
 }
 
 /* Process a DEFINE_CONSTRAINT, DEFINE_MEMORY_CONSTRAINT,
-   DEFINE_SPECIAL_MEMORY_CONSTRAINT, or DEFINE_ADDRESS_CONSTRAINT
-   expression, C.  */
+   DEFINE_SPECIAL_MEMORY_CONSTRAINT, DEFINE_RELAXED_MEMORY_CONSTRAINT, or
+   DEFINE_ADDRESS_CONSTRAINT expression, C.  */
 static void
 process_define_constraint (md_rtx_info *info)
 {
   add_constraint (XSTR (info->def, 0), 0, XEXP (info->def, 2),
 		  GET_CODE (info->def) == DEFINE_MEMORY_CONSTRAINT,
 		  GET_CODE (info->def) == DEFINE_SPECIAL_MEMORY_CONSTRAINT,
+		  GET_CODE (info->def) == DEFINE_RELAXED_MEMORY_CONSTRAINT,
 		  GET_CODE (info->def) == DEFINE_ADDRESS_CONSTRAINT,
 		  info->loc);
 }
@@ -971,7 +988,7 @@ static void
 process_define_register_constraint (md_rtx_info *info)
 {
   add_constraint (XSTR (info->def, 0), XSTR (info->def, 1),
-		  0, false, false, false, info->loc);
+		  0, false, false, false, false, info->loc);
 }
 
 /* Put the constraints into enum order.  We want to keep constraints
@@ -1011,6 +1028,12 @@ choose_enum_order (void)
       enum_order[next++] = c;
   special_memory_end = next;
 
+  relaxed_memory_start = next;
+  FOR_ALL_CONSTRAINTS (c)
+    if (c->is_relaxed_memory)
+      enum_order[next++] = c;
+  relaxed_memory_end = next;
+
   address_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (c->is_address)
@@ -1020,7 +1043,7 @@ choose_enum_order (void)
   maybe_allows_none_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& !c->maybe_allows_reg && !c->maybe_allows_mem)
       enum_order[next++] = c;
   maybe_allows_none_end = next;
@@ -1028,7 +1051,7 @@ choose_enum_order (void)
   maybe_allows_reg_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& c->maybe_allows_reg && !c->maybe_allows_mem)
       enum_order[next++] = c;
   maybe_allows_reg_end = next;
@@ -1036,14 +1059,14 @@ choose_enum_order (void)
   maybe_allows_mem_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& !c->maybe_allows_reg && c->maybe_allows_mem)
       enum_order[next++] = c;
   maybe_allows_mem_end = next;
 
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& c->maybe_allows_reg && c->maybe_allows_mem)
       enum_order[next++] = c;
   gcc_assert (next == num_constraints);
@@ -1466,6 +1489,8 @@ write_tm_preds_h (void)
 			    memory_start, memory_end);
       write_range_function ("insn_extra_special_memory_constraint",
 			    special_memory_start, special_memory_end);
+      write_range_function ("insn_extra_relaxed_memory_constraint",
+			    relaxed_memory_start, relaxed_memory_end);
       write_range_function ("insn_extra_address_constraint",
 			    address_start, address_end);
       write_allows_reg_mem_function ();
@@ -1515,6 +1540,7 @@ write_tm_preds_h (void)
 	    "  CT_CONST_INT,\n"
 	    "  CT_MEMORY,\n"
 	    "  CT_SPECIAL_MEMORY,\n"
+	    "  CT_RELAXED_MEMORY,\n"
 	    "  CT_ADDRESS,\n"
 	    "  CT_FIXED_FORM\n"
 	    "};\n"
@@ -1529,6 +1555,8 @@ write_tm_preds_h (void)
 	values.safe_push (std::make_pair (memory_start, "CT_MEMORY"));
       if (special_memory_start != special_memory_end)
 	values.safe_push (std::make_pair (special_memory_start, "CT_SPECIAL_MEMORY"));
+      if (relaxed_memory_start != relaxed_memory_end)
+	values.safe_push (std::make_pair (relaxed_memory_start, "CT_RELAXED_MEMORY"));
       if (address_start != address_end)
 	values.safe_push (std::make_pair (address_start, "CT_ADDRESS"));
       if (address_end != num_constraints)
@@ -1645,6 +1673,7 @@ main (int argc, const char **argv)
       case DEFINE_CONSTRAINT:
       case DEFINE_MEMORY_CONSTRAINT:
       case DEFINE_SPECIAL_MEMORY_CONSTRAINT:
+      case DEFINE_RELAXED_MEMORY_CONSTRAINT:
       case DEFINE_ADDRESS_CONSTRAINT:
 	process_define_constraint (&info);
 	break;
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index fdf4a9fdc1f..0f19bd70664 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -582,6 +582,7 @@ process_rtx (rtx desc, file_location loc)
     case DEFINE_REGISTER_CONSTRAINT:
     case DEFINE_MEMORY_CONSTRAINT:
     case DEFINE_SPECIAL_MEMORY_CONSTRAINT:
+    case DEFINE_RELAXED_MEMORY_CONSTRAINT:
     case DEFINE_ADDRESS_CONSTRAINT:
       queue_pattern (desc, &define_pred_tail, loc);
       break;
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index cf1d4992927..7547f3e0f53 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -780,6 +780,7 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
 		      break;
 
 		    case CT_SPECIAL_MEMORY:
+		    case CT_RELAXED_MEMORY:
 		      insn_allows_mem[i] = allows_mem[i] = 1;
 		      if (MEM_P (extract_mem_from_operand (op))
 			  && constraint_satisfied_p (op, cn))
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index f3341313bd1..bd1818bb255 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -872,6 +872,7 @@ single_reg_class (const char *constraints, rtx op, rtx equiv_const)
 	    cn = lookup_constraint (constraints);
 	    if (insn_extra_memory_constraint (cn)
 		|| insn_extra_special_memory_constraint (cn)
+		|| insn_extra_relaxed_memory_constraint (cn)
 		|| insn_extra_address_constraint (cn))
 	      return NO_REGS;
 	    if (constraint_satisfied_p (op, cn)
diff --git a/gcc/ira.c b/gcc/ira.c
index fc77131491d..7e903289e79 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -1874,6 +1874,7 @@ ira_setup_alts (rtx_insn *insn)
 			  mem = op;
 			  /* Fall through.  */
 			case CT_SPECIAL_MEMORY:
+			case CT_RELAXED_MEMORY:
 			  if (!mem)
 			    mem = extract_mem_from_operand (op);
 			  if (MEM_P (mem))
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index 64801b6fcce..d76d4d7162a 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -410,8 +410,7 @@ valid_address_p (rtx op, struct address_info *ad,
      Need to extract memory from op for special memory constraint,
      i.e. bcst_mem_operand in i386 backend.  */
   if (MEM_P (extract_mem_from_operand (op))
-      && (insn_extra_memory_constraint (constraint)
-	  || insn_extra_special_memory_constraint (constraint))
+      && insn_extra_relaxed_memory_constraint (constraint)
       && constraint_satisfied_p (op, constraint))
     return true;
 
@@ -2460,6 +2459,7 @@ process_alt_operands (int only_alternative)
 		      break;
 
 		    case CT_SPECIAL_MEMORY:
+		    case CT_RELAXED_MEMORY:
 		      if (satisfies_memory_constraint_p (op, cn))
 			win = true;
 		      else if (spilled_pseudo_p (op))
@@ -4365,7 +4365,8 @@ curr_insn_transform (bool check_only_p)
 	      {
 		enum constraint_num cn = lookup_constraint (constraint);
 		if ((insn_extra_memory_constraint (cn)
-		     || insn_extra_special_memory_constraint (cn))
+		     || insn_extra_special_memory_constraint (cn)
+		     || insn_extra_relaxed_memory_constraint (cn))
 		    && satisfies_memory_constraint_p (tem, cn))
 		  break;
 	      }
diff --git a/gcc/recog.c b/gcc/recog.c
index abbc49f3f9b..ee143bc761e 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -2270,6 +2270,7 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
 	      mem = op;
 	      /* Fall through.  */
 	    case CT_SPECIAL_MEMORY:
+	    case CT_RELAXED_MEMORY:
 	      /* Every memory operand can be reloaded to fit.  */
 	      if (!mem)
 		mem = extract_mem_from_operand (op);
@@ -2892,6 +2893,7 @@ preprocess_constraints (int n_operands, int n_alternatives,
 
 		    case CT_MEMORY:
 		    case CT_SPECIAL_MEMORY:
+		    case CT_RELAXED_MEMORY:
 		      op_alt[i].memory_ok = 1;
 		      break;
 
diff --git a/gcc/reload.c b/gcc/reload.c
index c88f928392b..7340125c441 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -3504,6 +3504,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
 			break;
 
 		      case CT_SPECIAL_MEMORY:
+		      case CT_RELAXED_MEMORY:
 			if (force_reload)
 			  break;
 			if (constraint_satisfied_p (operand, cn))
diff --git a/gcc/rtl.def b/gcc/rtl.def
index 92b3de822be..b85eb5c0055 100644
--- a/gcc/rtl.def
+++ b/gcc/rtl.def
@@ -1055,6 +1055,7 @@ DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RT
 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
 DEF_RTL_EXPR(DEFINE_SPECIAL_MEMORY_CONSTRAINT, "define_special_memory_constraint", "sse", RTX_EXTRA)
+DEF_RTL_EXPR(DEFINE_RELAXED_MEMORY_CONSTRAINT, "define_relaxed_memory_constraint", "sse", RTX_EXTRA)
 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
 
 
diff --git a/gcc/stmt.c b/gcc/stmt.c
index f52ffaf8e75..297e0d0ff5d 100644
--- a/gcc/stmt.c
+++ b/gcc/stmt.c
@@ -419,7 +419,8 @@ parse_input_constraint (const char **constraint_p, int input_num,
 	    || insn_extra_address_constraint (cn))
 	  *allows_reg = true;
 	else if (insn_extra_memory_constraint (cn)
-		 || insn_extra_special_memory_constraint (cn))
+		 || insn_extra_special_memory_constraint (cn)
+		 || insn_extra_relaxed_memory_constraint (cn))
 	  *allows_mem = true;
 	else
 	  insn_extra_constraint_allows_reg_mem (cn, allows_reg, allows_mem);
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99581.c b/gcc/testsuite/gcc.target/powerpc/pr99581.c
new file mode 100644
index 00000000000..525f2762773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr99581.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+char e[37540];
+struct A { int c; } d;
+
+void
+bar (int n)
+{
+  __asm__("" : : "r" (e));
+}
+
+void
+foo (void)
+{
+  __asm__("stw %1, %0" : "=o" (d.c) : "r" (0));
+}

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Alex Coplan]

Hi Vladimir,

On 19/03/2021 10:21, Vladimir Makarov via Gcc-patches wrote:
> The following patch solves P1 PR99581
> 
>     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
> 
> The patch was successfully tested and bootstrapped on x86-64, ppc64le,
> aarch64.
> 
> Is it ok for the trunk?

Can we avoid using the term "relaxed memory" here? The overlap with memory
models (as in relaxed memory concurrency) is rather misleading.

I'm not a maintainer, so this is just a suggestion.

Thanks,
Alex

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Jakub Jelinek]

On Fri, Mar 19, 2021 at 03:03:42PM +0000, Alex Coplan via Gcc-patches wrote:
> Hi Vladimir,
> 
> On 19/03/2021 10:21, Vladimir Makarov via Gcc-patches wrote:
> > The following patch solves P1 PR99581
> > 
> >     https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
> > 
> > The patch was successfully tested and bootstrapped on x86-64, ppc64le,
> > aarch64.
> > 
> > Is it ok for the trunk?
> 
> Can we avoid using the term "relaxed memory" here? The overlap with memory
> models (as in relaxed memory concurrency) is rather misleading.
> 
> I'm not a maintainer, so this is just a suggestion.

Relaxed memory sure, but relaxed memory constraint shouldn't be that
misleading, and that is what this patch adds.

	Jakub

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

On 2021-03-19 11:03 a.m., Alex Coplan wrote:
> Hi Vladimir,
>
> On 19/03/2021 10:21, Vladimir Makarov via Gcc-patches wrote:
>> The following patch solves P1 PR99581
>>
>>      https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
>>
>> The patch was successfully tested and bootstrapped on x86-64, ppc64le,
>> aarch64.
>>
>> Is it ok for the trunk?
> Can we avoid using the term "relaxed memory" here? The overlap with memory
> models (as in relaxed memory concurrency) is rather misleading.
>
I am open to rename if people propose a good alternative.

I had only one good alternative define_permissive_memory but it is longer.

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Richard Sandiford]

Vladimir Makarov via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> The following patch solves P1 PR99581
>
>      https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
>
> The patch was successfully tested and bootstrapped on x86-64, ppc64le, 
> aarch64.
>
> Is it ok for the trunk?

As I mentioned in bugzilla though, the motivation behind this seems
to be that "o" shouldn't need to check for a valid memory address,
even though "m" and "V" do:

--------------------------------------------------------------------------
(define_memory_constraint "TARGET_MEM_CONSTRAINT"
  "Matches any valid memory."
  (and (match_code "mem")
       (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
						 MEM_ADDR_SPACE (op))")))

(define_memory_constraint "o"
  "Matches an offsettable memory reference."
  (and (match_code "mem")
       (match_test "offsettable_nonstrict_memref_p (op)")))

;; "V" matches TARGET_MEM_CONSTRAINTs that are rejected by "o".
;; This means that it is not a memory constraint in the usual sense,
;; since reloading the address into a base register would make the
;; address offsettable.
(define_constraint "V"
  "Matches a non-offsettable memory reference."
  (and (match_code "mem")
       (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
						 MEM_ADDR_SPACE (op))")
       (not (match_test "offsettable_nonstrict_memref_p (op)"))))
--------------------------------------------------------------------------

If the model behind this is that memory constraints should be able
to assume basic validity (in the targetm.legitimate_address sense)
then it seems like "m" should just be:

--------------------------------------------------------------------------
(define_memory_constraint "TARGET_MEM_CONSTRAINT"
  "Matches any valid memory."
  (match_code "mem"))
--------------------------------------------------------------------------

But it seems to be long-established precedent that "m" isn't just that.

So I'm reluctant to go down this path if there's no clear reason why
"m" has to have the check but "o" doesn't.  I think we're also opening
the possiblity that we'll need a define_special_relaxed_memory_constraint
in future.

The reason why my LRA patch seemed OK to me was that we'd already done
the same thing for address constraints:

  /* Target hooks sometimes don't treat extra-constraint addresses as
     legitimate address_operands, so handle them specially.  */
  if (insn_extra_address_constraint (cn)
      && satisfies_address_constraint_p (&ad, cn))
    return change_p;

which ultimately came from:

  https://gcc.gnu.org/g:2c62cbaaf13c78f10657e91efdb8352dc8898b0d

and so is also long-standing precedent as this point.

So I think we should also have a model for why normal address constraints
can do this but normal memory constraints can't.

I'm not trying to reject the patch as such.  I just think we need to
have a clearer picture first.

Thanks,
Richard

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Jakub Jelinek]

On Fri, Mar 19, 2021 at 03:42:42PM +0000, Richard Sandiford via Gcc-patches wrote:
> Vladimir Makarov via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> > The following patch solves P1 PR99581
> >
> >      https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
> >
> > The patch was successfully tested and bootstrapped on x86-64, ppc64le, 
> > aarch64.
> >
> > Is it ok for the trunk?
> 
> As I mentioned in bugzilla though, the motivation behind this seems
> to be that "o" shouldn't need to check for a valid memory address,
> even though "m" and "V" do:

I'm just watching this from a distance, but I understood "o" is just one of
the many memory constraints that want such a behavior and that aarch64
UtQ is the only current known exception from that.  Isn't that the case?
So, if we fix "o", won't we run into it in a few days or weeks with many of
the other 160+ memory constraints?

	Jakub

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

On 2021-03-19 11:42 a.m., Richard Sandiford wrote:
> Vladimir Makarov via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
>> The following patch solves P1 PR99581
>>
>>       https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
>>
>> The patch was successfully tested and bootstrapped on x86-64, ppc64le,
>> aarch64.
>>
>> Is it ok for the trunk?
>
> I'm not trying to reject the patch as such.  I just think we need to
> have a clearer picture first.
>
I agree that 'o' should be treated as a subset of 'm' and therefore its 
definition should have a check as 'm' has.  Still my patch is not about 
treatment of constraint 'o' only.

My approach for LRA development is minimal changes, as radical changes 
(even if they look right) results long lasting unpredictable effects on 
many targets.

The patch in which you introduced a new function valid_address_p and new 
treatment of **all** memory constraints was too big change with this 
point of view and finally it resulted in this problem after recent 
partially fixing mess in process_address_1.

My patch fixes this radical change. So I think we still need the patch 
I've submitted.

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Richard Sandiford]

Vladimir Makarov <vmakarov@redhat.com> writes:
> On 2021-03-19 11:42 a.m., Richard Sandiford wrote:
>> Vladimir Makarov via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
>>> The following patch solves P1 PR99581
>>>
>>>       https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
>>>
>>> The patch was successfully tested and bootstrapped on x86-64, ppc64le,
>>> aarch64.
>>>
>>> Is it ok for the trunk?
>>
>> I'm not trying to reject the patch as such.  I just think we need to
>> have a clearer picture first.
>>
> I agree that 'o' should be treated as a subset of 'm' and therefore its 
> definition should have a check as 'm' has.  Still my patch is not about 
> treatment of constraint 'o' only.
>
> My approach for LRA development is minimal changes, as radical changes 
> (even if they look right) results long lasting unpredictable effects on 
> many targets.
>
> The patch in which you introduced a new function valid_address_p and new 
> treatment of **all** memory constraints was too big change with this 
> point of view and finally it resulted in this problem after recent 
> partially fixing mess in process_address_1.
>
> My patch fixes this radical change. So I think we still need the patch 
> I've submitted.

OK, fair enough.  I have some minor cosmetic comments below, but
otherwise the patch is OK for trunk and branch.

Thanks,
Richard

> diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
> index e3686dbfe61..90dd0401fa0 100644
> --- a/gcc/doc/md.texi
> +++ b/gcc/doc/md.texi
> @@ -4567,6 +4567,17 @@ The syntax and semantics are otherwise identical to
>  @code{define_constraint}.
>  @end deffn
 
> +@deffn {MD Expression} define_relaxed_memory_constraint name docstring exp
> +Usually memory address in @code{reload} pass is checked to be a legitimate
> +one besides checking the memory itself to satisfy the instruction
> +constraint.  Sometimes you need to avoid legitimate address check for
> +memory and use only check for memory to satisfy the constraint.  Use
> +this expression to describe operands for such cases.

How about something like:

-----------------------------------------------------------------------
The test expression in a @code{define_memory_constraint} can assume
that @code{TARGET_LEGITIMATE_ADDRESS_P} holds for the address inside
a @code{mem} rtx and so it does not need to test this condition itself.
In other words, a @code{define_memory_constraint} test of the form:

@smallexample
(match_test "mem")
@end smallexample

is enough to test whether an rtx is a @code{mem} @emph{and} whether
its address satisfies @code{TARGET_MEM_CONSTRAINT} (which is usually
@samp{'m'}).  Thus the conditions imposed by a @code{define_memory_constraint}
always apply on top of the conditions imposed by @code{TARGET_MEM_CONSTRAINT}.

However, it is sometimes useful to define memory constraints that allow
addresses beyond those accepted by @code{TARGET_LEGITIMATE_ADDRESS_P}.
@code{define_relaxed_memory_constraint} exists for this case.
The test expression in a @code{define_relaxed_memory_constraint} is
applied with no preconditions, so that the expression can determine
``from scratch'' exactly which addresses are valid and which are not.
-----------------------------------------------------------------------

> +
> +The syntax and semantics are otherwise identical to
> +@code{define_constraint}.

Think @code{define_memory_constraint} would be a better
reference point here.

> @@ -756,15 +759,15 @@ mangle (const char *name)
>    return XOBFINISH (rtl_obstack, const char *);
>  }
 
> -/* Add one constraint, of any sort, to the tables.  NAME is its name;
> -   REGCLASS is the register class, if any; EXP is the expression to
> -   test, if any; IS_MEMORY, IS_SPECIAL_MEMORY and IS_ADDRESS indicate
> -   memory, special memory, and address constraints, respectively; LOC
> -   is the .md file location.
> +/* Add one constraint, of any sort, to the tables.  NAME is its name; REGCLASS
> +   is the register class, if any; EXP is the expression to test, if any;
> +   IS_MEMORY, IS_SPECIAL_MEMORY, IS_RELAXED_MEMORY and IS_ADDRESS indicate
> +   memory, special memory, and address constraints, respectively; LOC is the .md

Long line.

> +   file location.
 
>     Not all combinations of arguments are valid; most importantly,
>     REGCLASS is mutually exclusive with EXP, and
> -   IS_MEMORY/IS_SPECIAL_MEMORY/IS_ADDRESS are only meaningful for
> +   IS_MEMORY/IS_SPECIAL_MEMORY/IS_RELAXED_MEMORY/IS_ADDRESS are only meaningful for

Same here.

>     constraints with EXP.
 
>     This function enforces all syntactic and semantic rules about what
> @@ -773,7 +776,7 @@ mangle (const char *name)
>  static void
>  add_constraint (const char *name, const char *regclass,
>  		rtx exp, bool is_memory, bool is_special_memory,
> -		bool is_address, file_location loc)
> +		bool is_relaxed_memory, bool is_address, file_location loc)
>  {
>    class constraint_data *c, **iter, **slot;
>    const char *p;
> @@ -895,6 +898,17 @@ add_constraint (const char *name, const char *regclass,
>  		      name, name[0]);
>  	  return;
>  	}
> +      else if (is_relaxed_memory)
> +	{
> +	  if (name[1] == '\0')
> +	    error_at (loc, "constraint letter '%c' cannot be a "
> +		      "relaxed memory constraint", name[0]);
> +	  else
> +	    error_at (loc, "constraint name '%s' begins with '%c', "
> +		      "and therefore cannot be a relaxed memory constraint",
> +		      name, name[0]);
> +	  return;
> +	}

I think we should just add “ || is_relaxed_memory” to the existing
“is_memory” condition (and should probably have done that with
is_special_memory).  We aren't making a distinction between
different types of memory constraint in this context; we're just
making a distinction between constant and non-constant constraints.

> @@ -1529,6 +1555,8 @@ write_tm_preds_h (void)
>  	values.safe_push (std::make_pair (memory_start, "CT_MEMORY"));
>        if (special_memory_start != special_memory_end)
>  	values.safe_push (std::make_pair (special_memory_start, "CT_SPECIAL_MEMORY"));
> +      if (relaxed_memory_start != relaxed_memory_end)
> +	values.safe_push (std::make_pair (relaxed_memory_start, "CT_RELAXED_MEMORY"));

Long line.

>        if (address_start != address_end)
>  	values.safe_push (std::make_pair (address_start, "CT_ADDRESS"));
>        if (address_end != num_constraints)

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

[-- Attachment #1: Type: text/plain, Size: 1597 bytes --]


On 2021-03-21 8:51 a.m., Richard Sandiford wrote:
> Vladimir Makarov <vmakarov@redhat.com> writes:
>> On 2021-03-19 11:42 a.m., Richard Sandiford wrote:
>>> Vladimir Makarov via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
>>>> The following patch solves P1 PR99581
>>>>
>>>>        https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
>>>>
>>>> The patch was successfully tested and bootstrapped on x86-64, ppc64le,
>>>> aarch64.
>>>>
>>>> Is it ok for the trunk?
>>> I'm not trying to reject the patch as such.  I just think we need to
>>> have a clearer picture first.
>>>
>> I agree that 'o' should be treated as a subset of 'm' and therefore its
>> definition should have a check as 'm' has.  Still my patch is not about
>> treatment of constraint 'o' only.
>>
>> My approach for LRA development is minimal changes, as radical changes
>> (even if they look right) results long lasting unpredictable effects on
>> many targets.
>>
>> The patch in which you introduced a new function valid_address_p and new
>> treatment of **all** memory constraints was too big change with this
>> point of view and finally it resulted in this problem after recent
>> partially fixing mess in process_address_1.
>>
>> My patch fixes this radical change. So I think we still need the patch
>> I've submitted.
> OK, fair enough.  I have some minor cosmetic comments below, but
> otherwise the patch is OK for trunk and branch.
>
Richard, thank you for your review and approval.  I incorporated all 
your proposals into the patch and committed it into the trunk.  The 
final patch is in the attachment.




[-- Attachment #2: pr99581-2.patch --]
[-- Type: text/x-patch, Size: 20395 bytes --]

commit fee6942d68924de9f30df313c46f37f811feea8a
Author: Vladimir N. Makarov <vmakarov@redhat.com>
Date:   Mon Mar 22 13:34:50 2021 -0400

    [PR99581] Define relaxed memory and use it for aarch64
    
    aarch64 needs to skip memory address validation for LD1R insns.  Skipping
    the address validation may result in LRA crash for some targets when usual
    memory constraint is used.  This patch introduces define_relaxed_memory_constraint,
    skipping address validation for it, and defining relaxed memory for
    aarch64 LD1r insn memory operand.
    
    gcc/ChangeLog:
    
            PR target/99581
            * config/aarch64/constraints.md (UtQ): Use
            define_relaxed_memory_constraint for it.
            * doc/md.text (define_relaxed_memory_constraint): Describe it.
            * genoutput.c (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * gepreds.c (constraint_data): Add bitfield is_relaxed_memory.
            (have_relaxed_memory_constraints): New static var.
            (relaxed_memory_start, relaxed_memory_end): Ditto.
            (add_constraint): Add arg is_relaxed_memory.  Check name for
            relaxed memory.  Set up is_relaxed_memory in constraint_data and
            have_relaxed_memory_constraints.  Adjust calls.
            (choose_enum_order): Process relaxed memory.
            (write_tm_preds_h): Ditto.
            (main): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * gensupport.c (process_rtx): Process DEFINE_RELAXED_MEMORY_CONSTRAINT.
            * ira-costs.c (record_reg_classes): Process CT_RELAXED_MEMORY.
            * ira-lives.c (single_reg_class): Use
            insn_extra_relaxed_memory_constraint.
            * ira.c (ira_setup_alts): CT_RELAXED_MEMORY.
            * lra-constraints.c (valid_address_p): Use
            insn_extra_relaxed_memory_constraint instead of other memory
            constraints.
            (process_alt_operands): Process CT_RELAXED_MEMORY.
            (curr_insn_transform): Use insn_extra_relaxed_memory_constraint.
            * recog.c (asm_operand_ok, preprocess_constraints): Process
            CT_RELAXED_MEMORY.
            * reload.c (find_reloads): Ditto.
            * rtl.def (DEFINE_RELAXED_MEMORY_CONSTRAINT): New.
            * gcc/stmt.c (parse_input_constraint): Use
            insn_extra_relaxed_memory_constraint.
    
    gcc/testsuite/ChangeLog:
    
            PR target/99581
            * gcc.target/powerpc/pr99581.c: New.

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 09c2b7283e3..f08eea8bcae 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -330,7 +330,7 @@
        (match_test "aarch64_legitimate_address_p (V2DImode,
 						  XEXP (op, 0), 1)")))
 
-(define_memory_constraint "UtQ"
+(define_relaxed_memory_constraint "UtQ"
   "@internal
    An address valid for SVE LD1RQs."
   (and (match_code "mem")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index e3686dbfe61..d166a0debed 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -4564,7 +4564,33 @@ specifically aligned memory is necessary or desirable for some insn
 operand.
 
 The syntax and semantics are otherwise identical to
-@code{define_constraint}.
+@code{define_memory_constraint}.
+@end deffn
+
+@deffn {MD Expression} define_relaxed_memory_constraint name docstring exp
+The test expression in a @code{define_memory_constraint} can assume
+that @code{TARGET_LEGITIMATE_ADDRESS_P} holds for the address inside
+a @code{mem} rtx and so it does not need to test this condition itself.
+In other words, a @code{define_memory_constraint} test of the form:
+
+@smallexample
+(match_test "mem")
+@end smallexample
+
+is enough to test whether an rtx is a @code{mem} @emph{and} whether
+its address satisfies @code{TARGET_MEM_CONSTRAINT} (which is usually
+@samp{'m'}).  Thus the conditions imposed by a @code{define_memory_constraint}
+always apply on top of the conditions imposed by @code{TARGET_MEM_CONSTRAINT}.
+
+However, it is sometimes useful to define memory constraints that allow
+addresses beyond those accepted by @code{TARGET_LEGITIMATE_ADDRESS_P}.
+@code{define_relaxed_memory_constraint} exists for this case.
+The test expression in a @code{define_relaxed_memory_constraint} is
+applied with no preconditions, so that the expression can determine
+``from scratch'' exactly which addresses are valid and which are not.
+
+The syntax and semantics are otherwise identical to
+@code{define_memory_constraint}.
 @end deffn
 
 @deffn {MD Expression} define_address_constraint name docstring exp
diff --git a/gcc/genoutput.c b/gcc/genoutput.c
index b88e13b90b6..25af4375d9c 100644
--- a/gcc/genoutput.c
+++ b/gcc/genoutput.c
@@ -1024,6 +1024,7 @@ main (int argc, const char **argv)
       case DEFINE_ADDRESS_CONSTRAINT:
       case DEFINE_MEMORY_CONSTRAINT:
       case DEFINE_SPECIAL_MEMORY_CONSTRAINT:
+      case DEFINE_RELAXED_MEMORY_CONSTRAINT:
 	note_constraint (&info);
 	break;
 
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 8499a2a2383..63fac0c7d34 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -660,9 +660,9 @@ write_one_predicate_function (struct pred_data *p)
 /* Constraints fall into two categories: register constraints
    (define_register_constraint), and others (define_constraint,
    define_memory_constraint, define_special_memory_constraint,
-   define_address_constraint).  We work out automatically which of the
-   various old-style macros they correspond to, and produce
-   appropriate code.  They all go in the same hash table so we can
+   define_relaxed_memory_constraint, define_address_constraint).  We work out
+   automatically which of the various old-style macros they correspond to, and
+   produce appropriate code.  They all go in the same hash table so we can
    verify that there are no duplicate names.  */
 
 /* All data from one constraint definition.  */
@@ -683,6 +683,7 @@ public:
   unsigned int is_extra		: 1;
   unsigned int is_memory	: 1;
   unsigned int is_special_memory: 1;
+  unsigned int is_relaxed_memory: 1;
   unsigned int is_address	: 1;
   unsigned int maybe_allows_reg : 1;
   unsigned int maybe_allows_mem : 1;
@@ -721,6 +722,7 @@ static unsigned int constraint_max_namelen;
 static bool have_register_constraints;
 static bool have_memory_constraints;
 static bool have_special_memory_constraints;
+static bool have_relaxed_memory_constraints;
 static bool have_address_constraints;
 static bool have_extra_constraints;
 static bool have_const_int_constraints;
@@ -732,6 +734,7 @@ static unsigned int satisfied_start;
 static unsigned int const_int_start, const_int_end;
 static unsigned int memory_start, memory_end;
 static unsigned int special_memory_start, special_memory_end;
+static unsigned int relaxed_memory_start, relaxed_memory_end;
 static unsigned int address_start, address_end;
 static unsigned int maybe_allows_none_start, maybe_allows_none_end;
 static unsigned int maybe_allows_reg_start, maybe_allows_reg_end;
@@ -756,16 +759,16 @@ mangle (const char *name)
   return XOBFINISH (rtl_obstack, const char *);
 }
 
-/* Add one constraint, of any sort, to the tables.  NAME is its name;
-   REGCLASS is the register class, if any; EXP is the expression to
-   test, if any; IS_MEMORY, IS_SPECIAL_MEMORY and IS_ADDRESS indicate
-   memory, special memory, and address constraints, respectively; LOC
-   is the .md file location.
+/* Add one constraint, of any sort, to the tables.  NAME is its name; REGCLASS
+   is the register class, if any; EXP is the expression to test, if any;
+   IS_MEMORY, IS_SPECIAL_MEMORY, IS_RELAXED_MEMORY and IS_ADDRESS indicate
+   memory, special memory, and address constraints, respectively; LOC is the .md
+   file location.
 
-   Not all combinations of arguments are valid; most importantly,
-   REGCLASS is mutually exclusive with EXP, and
-   IS_MEMORY/IS_SPECIAL_MEMORY/IS_ADDRESS are only meaningful for
-   constraints with EXP.
+   Not all combinations of arguments are valid; most importantly, REGCLASS is
+   mutually exclusive with EXP, and
+   IS_MEMORY/IS_SPECIAL_MEMORY/IS_RELAXED_MEMORY/IS_ADDRESS are only meaningful
+   for constraints with EXP.
 
    This function enforces all syntactic and semantic rules about what
    constraints can be defined.  */
@@ -773,7 +776,7 @@ mangle (const char *name)
 static void
 add_constraint (const char *name, const char *regclass,
 		rtx exp, bool is_memory, bool is_special_memory,
-		bool is_address, file_location loc)
+		bool is_relaxed_memory, bool is_address, file_location loc)
 {
   class constraint_data *c, **iter, **slot;
   const char *p;
@@ -873,7 +876,7 @@ add_constraint (const char *name, const char *regclass,
 	  return;
 	}
 
-      if (is_memory)
+      if (is_memory || is_special_memory || is_relaxed_memory)
 	{
 	  if (name[1] == '\0')
 	    error_at (loc, "constraint letter '%c' cannot be a "
@@ -884,17 +887,6 @@ add_constraint (const char *name, const char *regclass,
 		      name, name[0]);
 	  return;
 	}
-      else if (is_special_memory)
-	{
-	  if (name[1] == '\0')
-	    error_at (loc, "constraint letter '%c' cannot be a "
-		      "special memory constraint", name[0]);
-	  else
-	    error_at (loc, "constraint name '%s' begins with '%c', "
-		      "and therefore cannot be a special memory constraint",
-		      name, name[0]);
-	  return;
-	}
       else if (is_address)
 	{
 	  if (name[1] == '\0')
@@ -922,6 +914,7 @@ add_constraint (const char *name, const char *regclass,
   c->is_extra = !(regclass || is_const_int || is_const_dbl);
   c->is_memory = is_memory;
   c->is_special_memory = is_special_memory;
+  c->is_relaxed_memory = is_relaxed_memory;
   c->is_address = is_address;
   c->maybe_allows_reg = true;
   c->maybe_allows_mem = true;
@@ -949,19 +942,21 @@ add_constraint (const char *name, const char *regclass,
   have_extra_constraints |= c->is_extra;
   have_memory_constraints |= c->is_memory;
   have_special_memory_constraints |= c->is_special_memory;
+  have_relaxed_memory_constraints |= c->is_relaxed_memory;
   have_address_constraints |= c->is_address;
   num_constraints += 1;
 }
 
 /* Process a DEFINE_CONSTRAINT, DEFINE_MEMORY_CONSTRAINT,
-   DEFINE_SPECIAL_MEMORY_CONSTRAINT, or DEFINE_ADDRESS_CONSTRAINT
-   expression, C.  */
+   DEFINE_SPECIAL_MEMORY_CONSTRAINT, DEFINE_RELAXED_MEMORY_CONSTRAINT, or
+   DEFINE_ADDRESS_CONSTRAINT expression, C.  */
 static void
 process_define_constraint (md_rtx_info *info)
 {
   add_constraint (XSTR (info->def, 0), 0, XEXP (info->def, 2),
 		  GET_CODE (info->def) == DEFINE_MEMORY_CONSTRAINT,
 		  GET_CODE (info->def) == DEFINE_SPECIAL_MEMORY_CONSTRAINT,
+		  GET_CODE (info->def) == DEFINE_RELAXED_MEMORY_CONSTRAINT,
 		  GET_CODE (info->def) == DEFINE_ADDRESS_CONSTRAINT,
 		  info->loc);
 }
@@ -971,7 +966,7 @@ static void
 process_define_register_constraint (md_rtx_info *info)
 {
   add_constraint (XSTR (info->def, 0), XSTR (info->def, 1),
-		  0, false, false, false, info->loc);
+		  0, false, false, false, false, info->loc);
 }
 
 /* Put the constraints into enum order.  We want to keep constraints
@@ -1011,6 +1006,12 @@ choose_enum_order (void)
       enum_order[next++] = c;
   special_memory_end = next;
 
+  relaxed_memory_start = next;
+  FOR_ALL_CONSTRAINTS (c)
+    if (c->is_relaxed_memory)
+      enum_order[next++] = c;
+  relaxed_memory_end = next;
+
   address_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (c->is_address)
@@ -1020,7 +1021,7 @@ choose_enum_order (void)
   maybe_allows_none_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& !c->maybe_allows_reg && !c->maybe_allows_mem)
       enum_order[next++] = c;
   maybe_allows_none_end = next;
@@ -1028,7 +1029,7 @@ choose_enum_order (void)
   maybe_allows_reg_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& c->maybe_allows_reg && !c->maybe_allows_mem)
       enum_order[next++] = c;
   maybe_allows_reg_end = next;
@@ -1036,14 +1037,14 @@ choose_enum_order (void)
   maybe_allows_mem_start = next;
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& !c->maybe_allows_reg && c->maybe_allows_mem)
       enum_order[next++] = c;
   maybe_allows_mem_end = next;
 
   FOR_ALL_CONSTRAINTS (c)
     if (!c->is_register && !c->is_const_int && !c->is_memory
-	&& !c->is_special_memory && !c->is_address
+	&& !c->is_special_memory && !c->is_relaxed_memory && !c->is_address
 	&& c->maybe_allows_reg && c->maybe_allows_mem)
       enum_order[next++] = c;
   gcc_assert (next == num_constraints);
@@ -1466,6 +1467,8 @@ write_tm_preds_h (void)
 			    memory_start, memory_end);
       write_range_function ("insn_extra_special_memory_constraint",
 			    special_memory_start, special_memory_end);
+      write_range_function ("insn_extra_relaxed_memory_constraint",
+			    relaxed_memory_start, relaxed_memory_end);
       write_range_function ("insn_extra_address_constraint",
 			    address_start, address_end);
       write_allows_reg_mem_function ();
@@ -1515,6 +1518,7 @@ write_tm_preds_h (void)
 	    "  CT_CONST_INT,\n"
 	    "  CT_MEMORY,\n"
 	    "  CT_SPECIAL_MEMORY,\n"
+	    "  CT_RELAXED_MEMORY,\n"
 	    "  CT_ADDRESS,\n"
 	    "  CT_FIXED_FORM\n"
 	    "};\n"
@@ -1528,7 +1532,11 @@ write_tm_preds_h (void)
       if (memory_start != memory_end)
 	values.safe_push (std::make_pair (memory_start, "CT_MEMORY"));
       if (special_memory_start != special_memory_end)
-	values.safe_push (std::make_pair (special_memory_start, "CT_SPECIAL_MEMORY"));
+	values.safe_push (std::make_pair (special_memory_start,
+					  "CT_SPECIAL_MEMORY"));
+      if (relaxed_memory_start != relaxed_memory_end)
+	values.safe_push (std::make_pair (relaxed_memory_start,
+					  "CT_RELAXED_MEMORY"));
       if (address_start != address_end)
 	values.safe_push (std::make_pair (address_start, "CT_ADDRESS"));
       if (address_end != num_constraints)
@@ -1645,6 +1653,7 @@ main (int argc, const char **argv)
       case DEFINE_CONSTRAINT:
       case DEFINE_MEMORY_CONSTRAINT:
       case DEFINE_SPECIAL_MEMORY_CONSTRAINT:
+      case DEFINE_RELAXED_MEMORY_CONSTRAINT:
       case DEFINE_ADDRESS_CONSTRAINT:
 	process_define_constraint (&info);
 	break;
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index fdf4a9fdc1f..0f19bd70664 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -582,6 +582,7 @@ process_rtx (rtx desc, file_location loc)
     case DEFINE_REGISTER_CONSTRAINT:
     case DEFINE_MEMORY_CONSTRAINT:
     case DEFINE_SPECIAL_MEMORY_CONSTRAINT:
+    case DEFINE_RELAXED_MEMORY_CONSTRAINT:
     case DEFINE_ADDRESS_CONSTRAINT:
       queue_pattern (desc, &define_pred_tail, loc);
       break;
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index cf1d4992927..7547f3e0f53 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -780,6 +780,7 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
 		      break;
 
 		    case CT_SPECIAL_MEMORY:
+		    case CT_RELAXED_MEMORY:
 		      insn_allows_mem[i] = allows_mem[i] = 1;
 		      if (MEM_P (extract_mem_from_operand (op))
 			  && constraint_satisfied_p (op, cn))
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index f3341313bd1..bd1818bb255 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -872,6 +872,7 @@ single_reg_class (const char *constraints, rtx op, rtx equiv_const)
 	    cn = lookup_constraint (constraints);
 	    if (insn_extra_memory_constraint (cn)
 		|| insn_extra_special_memory_constraint (cn)
+		|| insn_extra_relaxed_memory_constraint (cn)
 		|| insn_extra_address_constraint (cn))
 	      return NO_REGS;
 	    if (constraint_satisfied_p (op, cn)
diff --git a/gcc/ira.c b/gcc/ira.c
index fc77131491d..7e903289e79 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -1874,6 +1874,7 @@ ira_setup_alts (rtx_insn *insn)
 			  mem = op;
 			  /* Fall through.  */
 			case CT_SPECIAL_MEMORY:
+			case CT_RELAXED_MEMORY:
 			  if (!mem)
 			    mem = extract_mem_from_operand (op);
 			  if (MEM_P (mem))
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index 64801b6fcce..d76d4d7162a 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -410,8 +410,7 @@ valid_address_p (rtx op, struct address_info *ad,
      Need to extract memory from op for special memory constraint,
      i.e. bcst_mem_operand in i386 backend.  */
   if (MEM_P (extract_mem_from_operand (op))
-      && (insn_extra_memory_constraint (constraint)
-	  || insn_extra_special_memory_constraint (constraint))
+      && insn_extra_relaxed_memory_constraint (constraint)
       && constraint_satisfied_p (op, constraint))
     return true;
 
@@ -2460,6 +2459,7 @@ process_alt_operands (int only_alternative)
 		      break;
 
 		    case CT_SPECIAL_MEMORY:
+		    case CT_RELAXED_MEMORY:
 		      if (satisfies_memory_constraint_p (op, cn))
 			win = true;
 		      else if (spilled_pseudo_p (op))
@@ -4365,7 +4365,8 @@ curr_insn_transform (bool check_only_p)
 	      {
 		enum constraint_num cn = lookup_constraint (constraint);
 		if ((insn_extra_memory_constraint (cn)
-		     || insn_extra_special_memory_constraint (cn))
+		     || insn_extra_special_memory_constraint (cn)
+		     || insn_extra_relaxed_memory_constraint (cn))
 		    && satisfies_memory_constraint_p (tem, cn))
 		  break;
 	      }
diff --git a/gcc/recog.c b/gcc/recog.c
index abbc49f3f9b..ee143bc761e 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -2270,6 +2270,7 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
 	      mem = op;
 	      /* Fall through.  */
 	    case CT_SPECIAL_MEMORY:
+	    case CT_RELAXED_MEMORY:
 	      /* Every memory operand can be reloaded to fit.  */
 	      if (!mem)
 		mem = extract_mem_from_operand (op);
@@ -2892,6 +2893,7 @@ preprocess_constraints (int n_operands, int n_alternatives,
 
 		    case CT_MEMORY:
 		    case CT_SPECIAL_MEMORY:
+		    case CT_RELAXED_MEMORY:
 		      op_alt[i].memory_ok = 1;
 		      break;
 
diff --git a/gcc/reload.c b/gcc/reload.c
index c88f928392b..7340125c441 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -3504,6 +3504,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
 			break;
 
 		      case CT_SPECIAL_MEMORY:
+		      case CT_RELAXED_MEMORY:
 			if (force_reload)
 			  break;
 			if (constraint_satisfied_p (operand, cn))
diff --git a/gcc/rtl.def b/gcc/rtl.def
index 92b3de822be..b85eb5c0055 100644
--- a/gcc/rtl.def
+++ b/gcc/rtl.def
@@ -1055,6 +1055,7 @@ DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RT
 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
 DEF_RTL_EXPR(DEFINE_SPECIAL_MEMORY_CONSTRAINT, "define_special_memory_constraint", "sse", RTX_EXTRA)
+DEF_RTL_EXPR(DEFINE_RELAXED_MEMORY_CONSTRAINT, "define_relaxed_memory_constraint", "sse", RTX_EXTRA)
 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
 
 
diff --git a/gcc/stmt.c b/gcc/stmt.c
index f52ffaf8e75..297e0d0ff5d 100644
--- a/gcc/stmt.c
+++ b/gcc/stmt.c
@@ -419,7 +419,8 @@ parse_input_constraint (const char **constraint_p, int input_num,
 	    || insn_extra_address_constraint (cn))
 	  *allows_reg = true;
 	else if (insn_extra_memory_constraint (cn)
-		 || insn_extra_special_memory_constraint (cn))
+		 || insn_extra_special_memory_constraint (cn)
+		 || insn_extra_relaxed_memory_constraint (cn))
 	  *allows_mem = true;
 	else
 	  insn_extra_constraint_allows_reg_mem (cn, allows_reg, allows_mem);
diff --git a/gcc/testsuite/gcc.target/powerpc/pr99581.c b/gcc/testsuite/gcc.target/powerpc/pr99581.c
new file mode 100644
index 00000000000..525f2762773
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr99581.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+char e[37540];
+struct A { int c; } d;
+
+void
+bar (int n)
+{
+  __asm__("" : : "r" (e));
+}
+
+void
+foo (void)
+{
+  __asm__("stw %1, %0" : "=o" (d.c) : "r" (0));
+}

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Christophe Lyon]

On Mon, 22 Mar 2021 at 18:38, Vladimir Makarov via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>
> On 2021-03-21 8:51 a.m., Richard Sandiford wrote:
> > Vladimir Makarov <vmakarov@redhat.com> writes:
> >> On 2021-03-19 11:42 a.m., Richard Sandiford wrote:
> >>> Vladimir Makarov via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> >>>> The following patch solves P1 PR99581
> >>>>
> >>>>        https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99581
> >>>>
> >>>> The patch was successfully tested and bootstrapped on x86-64, ppc64le,
> >>>> aarch64.
> >>>>
> >>>> Is it ok for the trunk?
> >>> I'm not trying to reject the patch as such.  I just think we need to
> >>> have a clearer picture first.
> >>>
> >> I agree that 'o' should be treated as a subset of 'm' and therefore its
> >> definition should have a check as 'm' has.  Still my patch is not about
> >> treatment of constraint 'o' only.
> >>
> >> My approach for LRA development is minimal changes, as radical changes
> >> (even if they look right) results long lasting unpredictable effects on
> >> many targets.
> >>
> >> The patch in which you introduced a new function valid_address_p and new
> >> treatment of **all** memory constraints was too big change with this
> >> point of view and finally it resulted in this problem after recent
> >> partially fixing mess in process_address_1.
> >>
> >> My patch fixes this radical change. So I think we still need the patch
> >> I've submitted.
> > OK, fair enough.  I have some minor cosmetic comments below, but
> > otherwise the patch is OK for trunk and branch.
> >
> Richard, thank you for your review and approval.  I incorporated all
> your proposals into the patch and committed it into the trunk.  The
> final patch is in the attachment.
>

Hi,

This patch causes regressions (116) on aarch64:
gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp
    gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
-fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
check-function-bodies ld1ro_bf16_112
    gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
-fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
check-function-bodies ld1ro_bf16_16
    gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
-fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
check-function-bodies ld1ro_bf16_index
    gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
-fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
check-function-bodies ld1ro_bf16_m128
    gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
-fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
check-function-bodies ld1ro_bf16_m16
[....]

Not sure why you didn't see them during your testing?

Can you check?

Thanks

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

On 2021-03-23 9:07 a.m., Christophe Lyon wrote:
> On Mon, 22 Mar 2021 at 18:38, Vladimir Makarov via Gcc-patches
> <gcc-patches@gcc.gnu.org> wrote:
>>
> Hi,
>
> This patch causes regressions (116) on aarch64:
> gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp
>      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> check-function-bodies ld1ro_bf16_112
>      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> check-function-bodies ld1ro_bf16_16
>      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> check-function-bodies ld1ro_bf16_index
>      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> check-function-bodies ld1ro_bf16_m128
>      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> check-function-bodies ld1ro_bf16_m16
> [....]
>
> Not sure why you didn't see them during your testing?
>
> Can you check?
>
Sorry, I've rerun (cd gcc && make check-gcc) on gcc114 for today trunk 
and I don't see the regressions mentioned above.

Can you check this too and if I am doing something wrong for testing, 
please point me out.

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Christophe Lyon]

On Tue, 23 Mar 2021 at 17:54, Vladimir Makarov <vmakarov@redhat.com> wrote:
>
>
> On 2021-03-23 9:07 a.m., Christophe Lyon wrote:
> > On Mon, 22 Mar 2021 at 18:38, Vladimir Makarov via Gcc-patches
> > <gcc-patches@gcc.gnu.org> wrote:
> >>
> > Hi,
> >
> > This patch causes regressions (116) on aarch64:
> > gcc.target/aarch64/sve/acle/aarch64-sve-acle-asm.exp
> >      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> > -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> > check-function-bodies ld1ro_bf16_112
> >      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> > -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> > check-function-bodies ld1ro_bf16_16
> >      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> > -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> > check-function-bodies ld1ro_bf16_index
> >      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> > -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> > check-function-bodies ld1ro_bf16_m128
> >      gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c  -std=gnu90 -O2
> > -fno-schedule-insns -DCHECK_ASM --save-temps -DTEST_FULL
> > check-function-bodies ld1ro_bf16_m16
> > [....]
> >
> > Not sure why you didn't see them during your testing?
> >
> > Can you check?
> >
> Sorry, I've rerun (cd gcc && make check-gcc) on gcc114 for today trunk
> and I don't see the regressions mentioned above.
>
> Can you check this too and if I am doing something wrong for testing,
> please point me out.
>

I'm testing with cross-compilers with ST hat, but I'm not the only one
seeing these failures, see gcc-testresults.
Andreas and in Linaro we are both testing native compilers.

These tests are driven by aarch64-sve-acle-asm.exp

Is it possible that the binutils version matters? I'm using 2.34 for
the cross-toolchains.

Christophe

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

On 2021-03-23 1:55 p.m., Christophe Lyon wrote:
> On Tue, 23 Mar 2021 at 17:54, Vladimir Makarov <vmakarov@redhat.com> wrote:
>>
>> Can you check?
>>
>> Sorry, I've rerun (cd gcc && make check-gcc) on gcc114 for today trunk
>> and I don't see the regressions mentioned above.
>>
>> Can you check this too and if I am doing something wrong for testing,
>> please point me out.
>>
> I'm testing with cross-compilers with ST hat, but I'm not the only one
> seeing these failures, see gcc-testresults.
> Andreas and in Linaro we are both testing native compilers.
>
> These tests are driven by aarch64-sve-acle-asm.exp
>
> Is it possible that the binutils version matters? I'm using 2.34 for
> the cross-toolchains.
>
Sorry, I looked at the tests in more details.  They require 
aarch64_asm_f64mm and gcc114.fsffrance.org is not that kind of machine.  
Therefore they are not even compiled on this machine. As I understand 
the tests should check the right assembler generation but the tests 
require to be run.

The problem can be in necessity to use more relaxed memory constraints 
for aarch64.

I'll investigate the regressions more.

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

[-- Attachment #1: Type: text/plain, Size: 1551 bytes --]


On 2021-03-23 2:24 p.m., Vladimir Makarov wrote:
>
> On 2021-03-23 1:55 p.m., Christophe Lyon wrote:
>> On Tue, 23 Mar 2021 at 17:54, Vladimir Makarov <vmakarov@redhat.com> 
>> wrote:
>>>
>>> Can you check?
>>>
>>> Sorry, I've rerun (cd gcc && make check-gcc) on gcc114 for today trunk
>>> and I don't see the regressions mentioned above.
>>>
>>> Can you check this too and if I am doing something wrong for testing,
>>> please point me out.
>>>
>> I'm testing with cross-compilers with ST hat, but I'm not the only one
>> seeing these failures, see gcc-testresults.
>> Andreas and in Linaro we are both testing native compilers.
>>
>> These tests are driven by aarch64-sve-acle-asm.exp
>>
>> Is it possible that the binutils version matters? I'm using 2.34 for
>> the cross-toolchains.
>>
> Sorry, I looked at the tests in more details.  They require 
> aarch64_asm_f64mm and gcc114.fsffrance.org is not that kind of 
> machine.  Therefore they are not even compiled on this machine. As I 
> understand the tests should check the right assembler generation but 
> the tests require to be run.
>
> The problem can be in necessity to use more relaxed memory constraints 
> for aarch64.
>
> I'll investigate the regressions more.
>
>

Here is the patch solving the problem.

Also although asm tests only checks assembler code, a lot of them use 
dg-require-effective-target and therefore can not be tested on other 
aarch64 machines.  So the patch removes them.

Richard, if the patch is ok, I could commit the patch.  Just let me 
know, please.



[-- Attachment #2: z --]
[-- Type: text/plain, Size: 53139 bytes --]

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index f08eea8b..fd3e925 100644
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -323,7 +323,7 @@
   (and (match_code "mem")
        (match_test "aarch64_simd_mem_operand_p (op)")))
 
-(define_memory_constraint "Utq"
+(define_relaxed_memory_constraint "Utq"
   "@internal
    An address valid for loading or storing a 128-bit AdvSIMD register"
   (and (match_code "mem")
@@ -336,32 +336,32 @@
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1rq_operand_p (op)")))
 
-(define_memory_constraint "UOb"
+(define_relaxed_memory_constraint "UOb"
   "@internal
    An address valid for SVE LD1ROH."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, QImode)")))
 
-(define_memory_constraint "UOh"
+(define_relaxed_memory_constraint "UOh"
   "@internal
    An address valid for SVE LD1ROH."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, HImode)")))
 
 
-(define_memory_constraint "UOw"
+(define_relaxed_memory_constraint "UOw"
   "@internal
    An address valid for SVE LD1ROW."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, SImode)")))
 
-(define_memory_constraint "UOd"
+(define_relaxed_memory_constraint "UOd"
   "@internal
    An address valid for SVE LD1ROD."
   (and (match_code "mem")
        (match_test "aarch64_sve_ld1ro_operand_p (op, DImode)")))
 
-(define_memory_constraint "Uty"
+(define_relaxed_memory_constraint "Uty"
   "@internal
    An address valid for SVE LD1Rs."
   (and (match_code "mem")
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_f32.c
index 376622d..635da34 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_lane_f32.c
index 0f624fe..45a80f5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_lane_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfdot_lane_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_f32.c
index 0f81011..b55fbc5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_lane_f32.c
index b0ec088..a4c25c7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_lane_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalb_lane_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_f32.c
index 2a583fa..44b28d9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_lane_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_lane_f32.c
index 3af3997..87870b2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_lane_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmlalt_lane_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmmla_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmmla_f32.c
index b1d98fb..9728005 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmmla_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/bfmmla_f32.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c
index d4f9150..2d9332f 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvt_bf16.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvtnt_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvtnt_bf16.c
index 54614c9..b097654 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvtnt_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/cvtnt_bf16.c
@@ -1,5 +1,5 @@
 /* { dg-additional-options "-march=armv8.2-a+sve+bf16" } */
-/* { dg-require-effective-target aarch64_asm_bf16_ok }  */
+
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
 #include "test_sve_acle.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c
index cb18017..4ff2571 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_bf16.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c
index 86081ed..771e2d4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f16.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c
index c8df00f..15b2614 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f32.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c
index 2fb9d5b..ea16cce 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_f64.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c
index 3cd211b..cd57401 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s16.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c
index 44b16ed..2b27c46 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s32.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c
index 3aa9a15..747c647 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s64.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c
index 49aff51..48c0d20 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_s8.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c
index 00bf9e12..ae6faa2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u16.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c
index 9e9b329..e8cefdd 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u32.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c
index 64ec628..ed4dea8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u64.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c
index 2270132..1154724 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/ld1ro_u8.c
@@ -1,6 +1,5 @@
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" { target { ! ilp32 } } } } */
 /* { dg-additional-options "-march=armv8.6-a+f64mm" } */
-/* { dg-require-effective-target aarch64_asm_f64mm_ok }  */
 
 #include "test_sve_acle.h"
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f32.c
index f66dbf3..2ee930a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f32mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f32mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f64.c
index 49dc060..961f943 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_s32.c
index e7ce009..91d3390 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_u32.c
index 81f5166..ab8925a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/mmla_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_lane_s32.c
index c6d74a4..46f6bc1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_lane_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_lane_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_s32.c
index 4b45261..a55334d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/sudot_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c
index f1810da..6c41534 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_bf16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f16.c
index 6420d0f..9a7a619 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f32.c
index 6fb2eec..aed2323 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f64.c
index e786a8d..8a45642 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s16.c
index 5483607..6dc8be2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s32.c
index ccb8319..f7dd15e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s64.c
index fe8125a..bbecaa8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s8.c
index 48040c1..f386a80 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_s8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u16.c
index 3657f91..efff4e2 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u32.c
index cc5ea28..48f0b17 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u64.c
index 4435b53..c3564da 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u8.c
index 4ebfedb..c8805c4 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn1q_u8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c
index 5623b54..3f8d3ff 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_bf16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f16.c
index db21909..37ecb46 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f32.c
index 1367a1e..575dc1a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f64.c
index 54325e7..bdbd5eb 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s16.c
index a0b6412..361f7fa 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s32.c
index 7c128c6..aa80326 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s64.c
index f222225..0ebba99 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s8.c
index bd5243f..6518d27 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_s8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u16.c
index 8da8563..07e3ff5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u32.c
index 6c0af02..76cfc92 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u64.c
index 857595c..57df2d3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u8.c
index 1fb85b2..f36578a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/trn2q_u8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_lane_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_lane_s32.c
index 8fd2556..1d0e4b8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_lane_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_lane_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_s32.c
index ccac5ca..510b62a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usdot_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usmmla_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usmmla_s32.c
index 9440f3f..7ad3732 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usmmla_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/usmmla_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_i8mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+sve+i8mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c
index 30a1992..38133fe 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_bf16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c
index c11e5bd..87461ab 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c
index d0ac945..d939ce1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c
index ac2e5c5..ad696be 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c
index aa200b2..1b3dada 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c
index eb849df..39d5987 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c
index e104976..5fec3e5 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c
index 8aa5921..1ed1b2c 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_s8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c
index 00ffaab..9c3aaea 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c
index cd2e4db..b73ff77 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c
index 7d88233..d8467b8 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c
index 701a1d5..556a543 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp1q_u8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c
index bbac53a..c0c9024 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_bf16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c
index e19d118..c3b4231 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c
index af7112b..679b19d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c
index 4109b84..37c49e1 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c
index 0c6ab25..e25ec13 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c
index 9b914e70..65e8f78 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c
index 697e37d..a4d504b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c
index 576262c..ba9d85e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_s8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c
index f2debc2..0040a2d 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c
index ad6a4bc..c0c9431 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c
index a846aa2..90290aa 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c
index 163c226..8e3a3ea 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/uzp2q_u8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c
index aabf7c0..4e5699a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_bf16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f16.c
index 1170cc5..c932565 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f32.c
index 09666da..4e50242 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f64.c
index d77fb1c..9d3453a 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s16.c
index 92a6b55..9cc5fc3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s32.c
index a918d2d..73fa1b0 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s64.c
index be3524f..da4fefe 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s8.c
index 24ea239..eea43ae 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_s8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u16.c
index 65caf97..14db8de 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u32.c
index abd76b7..a8b0b08 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u64.c
index 0e91929..079ef11 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u8.c
index 07d484b..104d14e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip1q_u8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c
index 6d79136..18da6c3 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_bf16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f16.c
index 984240e..b55cc68 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f32.c
index 0f8ccd8..4d1ee76 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f64.c
index b5411cf..c89b5e9 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_f64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s16.c
index 66751fc..6390c11 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s32.c
index 830de33..9de850e 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s64.c
index 917be4f..5bc0076 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s8.c
index dff6e2d..ebaccc7 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_s8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u16.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u16.c
index 9e19442..e7225cc 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u16.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u16.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u32.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u32.c
index 89de27f..d4b9bc0 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u32.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u32.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u64.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u64.c
index f2c9852..9946198 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u64.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u64.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 
diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u8.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u8.c
index a129055..4660b1b 100644
--- a/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u8.c
+++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/asm/zip2q_u8.c
@@ -1,4 +1,4 @@
-/* { dg-require-effective-target aarch64_asm_f64mm_ok } */
+
 /* { dg-additional-options "-march=armv8.2-a+f64mm" } */
 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
 

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Richard Sandiford]

Vladimir Makarov <vmakarov@redhat.com> writes:
> On 2021-03-23 2:24 p.m., Vladimir Makarov wrote:
>>
>> On 2021-03-23 1:55 p.m., Christophe Lyon wrote:
>>> On Tue, 23 Mar 2021 at 17:54, Vladimir Makarov <vmakarov@redhat.com> 
>>> wrote:
>>>>
>>>> Can you check?
>>>>
>>>> Sorry, I've rerun (cd gcc && make check-gcc) on gcc114 for today trunk
>>>> and I don't see the regressions mentioned above.
>>>>
>>>> Can you check this too and if I am doing something wrong for testing,
>>>> please point me out.
>>>>
>>> I'm testing with cross-compilers with ST hat, but I'm not the only one
>>> seeing these failures, see gcc-testresults.
>>> Andreas and in Linaro we are both testing native compilers.
>>>
>>> These tests are driven by aarch64-sve-acle-asm.exp
>>>
>>> Is it possible that the binutils version matters? I'm using 2.34 for
>>> the cross-toolchains.
>>>
>> Sorry, I looked at the tests in more details.  They require 
>> aarch64_asm_f64mm and gcc114.fsffrance.org is not that kind of 
>> machine.  Therefore they are not even compiled on this machine. As I 
>> understand the tests should check the right assembler generation but 
>> the tests require to be run.
>>
>> The problem can be in necessity to use more relaxed memory constraints 
>> for aarch64.
>>
>> I'll investigate the regressions more.
>>
>>
>
> Here is the patch solving the problem.
>
> Also although asm tests only checks assembler code, a lot of them use 
> dg-require-effective-target and therefore can not be tested on other 
> aarch64 machines.  So the patch removes them.

I think they're still needed.  The harness tries to use assemble
rather than compile tests by default, so that the assembler picks
up any invalid instructions.  However, we can't assume that everyone
has a version of binutils that supports SVE and .variant_pcs, so the
tests fall back to compile tests unless:

if { [check_effective_target_aarch64_asm_sve_ok]
     && [check_effective_target_aarch64_variant_pcs] } {

is true.

However, the same problem then occurs for features that were added
by later architecture revisions, such as the ones being tested here.
Not everyone will have an assembler that understands these newer
instructions.

So the dg-require-effective-target are needed for the case in which
the system assembler is recent enough to support SVE but is not
recent enough to support these other extensions.

In other words, it wasn't your fault that these regressions didn't
show up.  But the fact that they didn't show up is kind-of deliberate,
since the testing provided by the assembler is a really useful sanity
check in this context.

The constraints.md patch is OK though.  Thanks for the quick fix.

Richard

Re: [PATCH] [PR99581] Define relaxed memory and use it for aarch64

[Vladimir Makarov]

On 2021-03-23 5:33 p.m., Richard Sandiford wrote:
> Vladimir Makarov <vmakarov@redhat.com> writes:
>> On 2021-03-23 2:24 p.m., Vladimir Makarov wrote:
>>>
>> Here is the patch solving the problem.
>>
>> Also although asm tests only checks assembler code, a lot of them use
>> dg-require-effective-target and therefore can not be tested on other
>> aarch64 machines.  So the patch removes them.
> I think they're still needed.  The harness tries to use assemble
> rather than compile tests by default, so that the assembler picks
> up any invalid instructions.  However, we can't assume that everyone
> has a version of binutils that supports SVE and .variant_pcs, so the
> tests fall back to compile tests unless:
>
> if { [check_effective_target_aarch64_asm_sve_ok]
>       && [check_effective_target_aarch64_variant_pcs] } {
>
> is true.
>
> However, the same problem then occurs for features that were added
> by later architecture revisions, such as the ones being tested here.
> Not everyone will have an assembler that understands these newer
> instructions.
>
> So the dg-require-effective-target are needed for the case in which
> the system assembler is recent enough to support SVE but is not
> recent enough to support these other extensions.
>
> In other words, it wasn't your fault that these regressions didn't
> show up.  But the fact that they didn't show up is kind-of deliberate,
> since the testing provided by the assembler is a really useful sanity
> check in this context.
>
> The constraints.md patch is OK though.  Thanks for the quick fix.
>
Thanks for the explanation, Richard.

I think it would be nice to have a check for binutils instead of 
effective target.  Otherwise, the same situation can be repeated in the 
future.  Although I don't know how to implement this in dejagnu.

In any case, I've committed the patch with changes only in constraints.md.