From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 88397 invoked by alias); 5 Sep 2019 09:21:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 88388 invoked by uid 89); 5 Sep 2019 09:21:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-10.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_SHORT autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 05 Sep 2019 09:21:54 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 61B231576; Thu, 5 Sep 2019 02:21:51 -0700 (PDT) Received: from e120077-lin.cambridge.arm.com (e120077-lin.cambridge.arm.com [10.2.206.91]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CABF03F67D; Thu, 5 Sep 2019 02:21:49 -0700 (PDT) Subject: Re: [PATCHv5] Fix not 8-byte aligned ldrd/strd on ARMv5 (PR 89544) From: "Richard Earnshaw (lists)" To: Bernd Edlinger , Richard Biener Cc: "gcc-patches@gcc.gnu.org" , Ramana Radhakrishnan , Kyrill Tkachov , Eric Botcazou , Jeff Law , Jakub Jelinek References: <1806cfa6-30c6-0719-0c4d-0fc56accd5e7@arm.com> Message-ID: Date: Thu, 05 Sep 2019 09:21:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-SW-Source: 2019-09/txt/msg00254.txt.bz2 On 04/09/2019 16:48, Richard Earnshaw (lists) wrote: > On 04/09/2019 16:00, Bernd Edlinger wrote: >> On 9/4/19 4:14 PM, Richard Earnshaw (lists) wrote: >>> On 04/09/2019 14:28, Bernd Edlinger wrote: >>>> On 9/4/19 2:53 PM, Richard Earnshaw (lists) wrote: >>>>> Index: gcc/testsuite/gcc.target/arm/unaligned-argument-2.c >>>>> =================================================================== >>>>> --- gcc/testsuite/gcc.target/arm/unaligned-argument-2.c >>>>> (Revision 0) >>>>> +++ gcc/testsuite/gcc.target/arm/unaligned-argument-2.c >>>>> (Arbeitskopie) >>>>> @@ -0,0 +1,19 @@ >>>>> +/* { dg-do compile } */ >>>>> +/* { dg-require-effective-target arm_arm_ok } */ >>>>> +/* { dg-require-effective-target arm_ldrd_strd_ok } */ >>>>> +/* { dg-options "-marm -mno-unaligned-access -O3" } */ >>>>> + >>>>> +struct s { >>>>> +  int a, b; >>>>> +} __attribute__((aligned(8))); >>>>> + >>>>> +struct s f0; >>>>> + >>>>> +void f(int a, int b, int c, int d, int e, struct s f) >>>>> +{ >>>>> +  f0 = f; >>>>> +} >>>>> + >>>>> +/* { dg-final { scan-assembler-times "ldrd" 0 } } */ >>>>> +/* { dg-final { scan-assembler-times "strd" 0 } } */ >>>>> +/* { dg-final { scan-assembler-times "stm" 1 } } */ >>>>> >>>>> I don't think this test is right.  While we can't use an LDRD to >>>>> load the argument off the stack, there's nothing wrong with using >>>>> an STRD to then store the value to f0 (as that is 8-byte aligned). >>>>> So the second and third scan-assembler tests are meaningless. >>>>> >>>> >>>> Ah, that is very similar to the unaligned-memcpy-2/3.c, >>>> see https://gcc.gnu.org/ml/gcc-patches/2019-09/msg00157.html >>>> >>>> initially that is a movdi, >>>> then in subreg1 it is split in two movsi >>>> which is then re-assembled as ldm >>>> >>>> >>>> Not sure if that is intended in that way. >>>> >>>> >>> >>> Yeah, these are causing me some problems too, but that's because with >>> some changes I'm working on I now see the compiler using r4 and r5, >>> which leads to prologue and epilogue stores that distort the results. >>> >>> Tests like this are generally fragile - I hate 'em!!!! >>> >> >> Yeah, that changed since r275063 introduced the unaligned-load/storedi >> >> r275063 | edlinger | 2019-08-30 12:38:37 +0200 (Fr, 30. Aug 2019) | 10 >> Zeilen >> Geänderte Pfade: >>     M /trunk/gcc/ChangeLog >>     M /trunk/gcc/config/arm/arm.c >>     M /trunk/gcc/config/arm/arm.md >>     M /trunk/gcc/config/arm/neon.md >> >> 2019-08-30  Bernd Edlinger  >> >>          * config/arm/arm.md (unaligned_loaddi, >>          unaligned_storedi): New unspec insn patterns. >>          * config/arm/neon.md (unaligned_storev8qi): Likewise. >>          * config/arm/arm.c (gen_cpymem_ldrd_strd): Use unaligned_loaddi >>          and unaligned_storedi for 4-byte aligned memory. >>          (arm_block_set_aligned_vect): Use unaligned_storev8qi for >>          4-byte aligned memory. >> >> Since other than the movdi they are not split up but stay as ldrd/strd. >> But for some unknown reason ira assigns r4-5 to those although also >> r1-2 would be available. :-( >> > > r1-r2 can't be used in Arm state as the register has to start on an even > boundary.  But ira has already used r3 for the address of the store (it > could have picked r1) and now r4-r5 is the next even-numbered pair.  So > we end up with needing to save some call-clobbered regs. > > R. >> >> Bernd. >> > One possible trick to stabilize the test is to insert an asm that clobbers r4 and r5 and forces the prologue/epilogue code to always save and restore them. Then we can account for those prologue/epilogue consistently (at least, modulo the arm_prefer_ldrd_strd condition). R.