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([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id h5-20020aa79f45000000b0056ca3569a66sm273941pfr.129.2022.10.28.21.33.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Oct 2022 21:33:55 -0700 (PDT) Message-ID: Date: Fri, 28 Oct 2022 22:33:50 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Subject: Re: [PATCH v4] RISC-V: Libitm add RISC-V support. Content-Language: en-US To: Xiongchuan Tan , gcc-patches@gcc.gnu.org Cc: fantasquex@gmail.com, Andrew Waterman , Kito Cheng References: From: Jeff Law In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 10/28/22 06:34, Xiongchuan Tan via Gcc-patches wrote: > Reviewed-by: Palmer Dabbelt > Acked-by: Palmer Dabbelt > > libitm/ChangeLog: > > * configure.tgt: Add riscv support. > * config/riscv/asm.h: New file. > * config/riscv/sjlj.S: New file. > * config/riscv/target.h: New file. > --- > v2: Change HW_CACHELINE_SIZE to 64 (in accordance with the RVA profiles, see > https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc) > > v3: Ensure the stack is aligned to 16 bytes; make use of Zihintpause in > cpu_relax() > > v4: Add a guard for unsupported RV32E > > libitm/config/riscv/asm.h | 58 ++++++++++++++ > libitm/config/riscv/sjlj.S | 144 +++++++++++++++++++++++++++++++++++ > libitm/config/riscv/target.h | 62 +++++++++++++++ > libitm/configure.tgt | 2 + > 4 files changed, 266 insertions(+) > create mode 100644 libitm/config/riscv/asm.h > create mode 100644 libitm/config/riscv/sjlj.S > create mode 100644 libitm/config/riscv/target.h > > diff --git a/libitm/config/riscv/asm.h b/libitm/config/riscv/asm.h > new file mode 100644 > index 0000000..8d02117 > --- /dev/null > +++ b/libitm/config/riscv/asm.h > @@ -0,0 +1,58 @@ > +/* Copyright (C) 2022 Free Software Foundation, Inc. > + Contributed by Xiongchuan Tan . > + > + This file is part of the GNU Transactional Memory Library (libitm). > + > + Libitm is free software; you can redistribute it and/or modify it > + under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3 of the License, or > + (at your option) any later version. > + > + Libitm is distributed in the hope that it will be useful, but WITHOUT ANY > + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS > + FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + more details. > + > + Under Section 7 of GPL version 3, you are granted additional > + permissions described in the GCC Runtime Library Exception, version > + 3.1, as published by the Free Software Foundation. > + > + You should have received a copy of the GNU General Public License and > + a copy of the GCC Runtime Library Exception along with this program; > + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > + . */ > + > +#ifndef _RV_ASM_H > +#define _RV_ASM_H > + > +#ifdef __riscv_e > +# error "rv32e unsupported" > +#endif error "rv32e and rv64e unsupported" would probably be a better error here.  But it's probably not a big deal. > +#else > +# define SZ_FPR 0 > +#endif Sneaky way to not allocate space for the FP regs.  ;) Do you have commit access?  If so, go ahead and commit the change.  Else let me know and I can do it for you. Thanks, Jeff