From: Richard Henderson <rth@twiddle.net>
To: James Greenhalgh <james.greenhalgh@arm.com>,
Richard Henderson <richard.henderson@linaro.org>
Cc: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
Ramana Radhakrishnan <Ramana.Radhakrishnan@arm.com>,
"agraf@suse.de" <agraf@suse.de>,
Marcus Shawcroft <Marcus.Shawcroft@arm.com>,
Richard Earnshaw <Richard.Earnshaw@arm.com>,
nd@arm.com, will.deacon@arm.com
Subject: Re: [PATCH, AArch64 v2 05/11] aarch64: Emit LSE st<op> instructions
Date: Wed, 31 Oct 2018 11:13:00 -0000 [thread overview]
Message-ID: <d4c24539-9f37-244f-ff72-88c2fb48a4a3@twiddle.net> (raw)
In-Reply-To: <20181030203228.GC22348@arm.com>
On 10/30/18 8:32 PM, James Greenhalgh wrote:
> On Tue, Oct 02, 2018 at 11:19:09AM -0500, Richard Henderson wrote:
>> When the result of an operation is not used, we can ignore the
>> result by storing to XZR. For two of the memory models, using
>> XZR with LD<op> has a preferred assembler alias, ST<op>.
>
> ST<op> has different semantics to LD<op>, in particular, ST<op> is not
> ordered by a DMB LD; so this could weaken the LDADD and break C11 semantics.
>
> The relevant Arm Arm text is:
>
> If the destination register is not one of WZR or XZR, LDADDA and
> LDADDAL load from memory with acquire semantics
You're quite right. I must have glossed over that clause when looking at this
before. I'll make sure there's a temp register to clobber for v2.
r~
next prev parent reply other threads:[~2018-10-31 10:09 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 16:19 [PATCH, AArch64 v2 00/11] LSE atomics out-of-line Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 11/11] Enable -matomic-ool by default Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 07/11] aarch64: Add out-of-line functions for LSE atomics Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 02/11] aarch64: Improve cas generation Richard Henderson
2018-10-30 20:37 ` James Greenhalgh
2018-10-02 16:19 ` [PATCH, AArch64 v2 09/11] aarch64: Force TImode values into even registers Richard Henderson
2018-10-30 21:47 ` James Greenhalgh
2018-10-02 16:19 ` [PATCH, AArch64 v2 01/11] aarch64: Simplify LSE cas generation Richard Henderson
2018-10-30 20:32 ` James Greenhalgh
2018-10-31 10:35 ` Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 04/11] aarch64: Improve atomic-op lse generation Richard Henderson
2018-10-30 21:40 ` James Greenhalgh
2018-10-02 16:19 ` [PATCH, AArch64 v2 08/11] aarch64: Implement -matomic-ool Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 03/11] aarch64: Improve swp generation Richard Henderson
2018-10-30 20:50 ` James Greenhalgh
2018-10-02 16:19 ` [PATCH, AArch64 v2 06/11] Add visibility to libfunc constructors Richard Henderson
2018-10-30 21:46 ` James Greenhalgh
2018-10-31 11:29 ` Richard Henderson
2018-10-31 17:46 ` Eric Botcazou
2018-10-31 19:04 ` Richard Henderson
2018-10-31 19:43 ` Eric Botcazou
2018-10-02 16:36 ` [PATCH, AArch64 v2 10/11] aarch64: Implement TImode compare-and-swap Richard Henderson
2018-10-02 16:37 ` [PATCH, AArch64 v2 05/11] aarch64: Emit LSE st<op> instructions Richard Henderson
2018-10-30 21:42 ` James Greenhalgh
2018-10-31 11:13 ` Richard Henderson [this message]
2018-10-31 11:25 ` Richard Henderson
2018-10-31 15:49 ` Will Deacon
2018-10-31 17:35 ` Richard Henderson
2018-10-31 19:42 ` Will Deacon
2018-10-31 22:39 ` Richard Henderson
2018-10-11 17:44 ` [PATCH, AArch64 v2 00/11] LSE atomics out-of-line Richard Henderson
2018-10-22 14:01 ` Richard Henderson
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