On 4/26/23 14:45, Bernhard Reutner-Fischer wrote:
> On 26 April 2023 23:21:06 CEST, Patrick O'Neill<patrick@rivosinc.com>  wrote:
>> This patch fixes whitespace errors introduced with
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
>>
>> 2023-04-26 Patrick O'Neill<patrick@rivosinc.com>
>>
>> gcc/ChangeLog:
>>
>> 	* config/riscv/riscv.cc: Fix whitespace.
>> 	* config/riscv/sync.md: Fix whitespace.
> The .md change above is gone by now.

There are still some sync.md changes (comment whitespace/function whitespace changes).

> No reason to resend the patch, just fixing it before you push it is fine, once ACKed (although such patches usually counts as obvious).

Thanks for the help with this - still getting the hang of pushing my own changes!

Patrick

> Many thanks for the quick tweak!
> cheers,
>
>> Signed-off-by: Patrick O'Neill<patrick@rivosinc.com>
>> ---
>> Patch was checked with contrib/check_GNU_style.py
>>
>> Whitespace changes in this patch are 2 flavors:
>> * Add space between function name and ()
>> * 2 spaces between end of comment and  */
>> ---
>> v2 Changelog:
>> * Ignored checker warning for space before [] in rtl
>> ---
>> gcc/config/riscv/riscv.cc |  6 +++---
>> gcc/config/riscv/sync.md  | 16 ++++++++--------
>> 2 files changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 0f890469d7a..1529855a2b4 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask,
>>    emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask,
>> 					 gen_lowpart (QImode, *shift)));
>>
>> -  emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask));
>> +  emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask));
>> }
>>
>> /* Leftshift a subword within an SImode register.  */
>> @@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift,
>>    emit_move_insn (value_reg, simplify_gen_subreg (SImode, value,
>> 						  mode, 0));
>>
>> -  emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
>> -						 gen_lowpart (QImode, shift)));
>> +  emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
>> +						  gen_lowpart (QImode, shift)));
>> }
>>
>> /* Initialize the GCC target structure.  */
>> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
>> index 83be6431cb6..19274528262 100644
>> --- a/gcc/config/riscv/sync.md
>> +++ b/gcc/config/riscv/sync.md
>> @@ -128,10 +128,10 @@
>> {
>>    /* We have no QImode/HImode atomics, so form a mask, then use
>>       subword_atomic_fetch_strong_nand to implement a LR/SC version of the
>> -     operation. */
>> +     operation.  */
>>
>>    /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
>> -     is disabled */
>> +     is disabled.  */
>>
>>    rtx old = gen_reg_rtx (SImode);
>>    rtx mem = operands[1];
>> @@ -193,10 +193,10 @@
>> {
>>    /* We have no QImode/HImode atomics, so form a mask, then use
>>       subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
>> -     operation. */
>> +     operation.  */
>>
>>    /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
>> -     is disabled */
>> +     is disabled.  */
>>
>>    rtx old = gen_reg_rtx (SImode);
>>    rtx mem = operands[1];
>> @@ -367,7 +367,7 @@
>>      {
>>        rtx difference = gen_rtx_MINUS (SImode, val, exp);
>>        compare = gen_reg_rtx (SImode);
>> -      emit_move_insn  (compare, difference);
>> +      emit_move_insn (compare, difference);
>>      }
>>
>>    if (word_mode != SImode)
>> @@ -393,10 +393,10 @@
>> {
>>    /* We have no QImode/HImode atomics, so form a mask, then use
>>       subword_atomic_cas_strong<mode> to implement a LR/SC version of the
>> -     operation. */
>> +     operation.  */
>>
>>    /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
>> -     is disabled */
>> +     is disabled.  */
>>
>>    rtx old = gen_reg_rtx (SImode);
>>    rtx mem = operands[1];
>> @@ -461,7 +461,7 @@
>>    "TARGET_ATOMIC"
>> {
>>    /* We have no QImode atomics, so use the address LSBs to form a mask,
>> -     then use an aligned SImode atomic. */
>> +     then use an aligned SImode atomic.  */
>>    rtx result = operands[0];
>>    rtx mem = operands[1];
>>    rtx model = operands[2];
>> --
>> 2.34.1
>>