From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf1-x441.google.com (mail-pf1-x441.google.com [IPv6:2607:f8b0:4864:20::441]) by sourceware.org (Postfix) with ESMTPS id AE9973858D3C for ; Wed, 26 Apr 2023 21:59:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AE9973858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pf1-x441.google.com with SMTP id d2e1a72fcca58-63b5465fb99so6401230b3a.1 for ; Wed, 26 Apr 2023 14:59:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20221208.gappssmtp.com; s=20221208; t=1682546378; x=1685138378; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:from:to:cc:subject:date :message-id:reply-to; bh=Lie1ciO/P9rGsVpvtzaqcajmZ/13TuO9VUkpvaQaSHY=; b=gFl2K0mLbEfy+rU/Jaj4GLEVN3D5VSM2Auzm1IzBNiSjEBaYKqgnRlfv0rEBziRUr/ LabfsWQih0Kgv5GywlkBy9xPRXf2ewOUpgnASCvzjwzGXoWZ3WxUb66dKp2Jym2QHlpE 0gKg2pQc6uA5wUyzP7dYvMOXKOOGsFenHfWOPLWfinUzHqShNA0/LuuCEco8BY8SNucU rEYTmmpL95fzDJGbo9gMG016JsAmOQsACiMDl0lWD/G/hIHBQ4FewnMSmJzo97c4jbnp llqzTvU7ca82uHi1sT2E5MdNi87RJFDD0Xmalk0qDqtx/1+DYxNA1rXPY5JxtJBfGH4B u37A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682546378; x=1685138378; h=in-reply-to:from:references:cc:to:content-language:subject :user-agent:mime-version:date:message-id:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=Lie1ciO/P9rGsVpvtzaqcajmZ/13TuO9VUkpvaQaSHY=; b=fPtC991Jv2PlwsjrBsUuHBeiqvCrv3yngsm+AP1uhXH4LqmKfrTC2yJFmiAUXCdzg0 G/DQlZDIA1y4WCNeEk4WkMZbP3iOa+TBEzLBByLkBAF8SJMjknroZLhNH4AZy2q4gW94 9xKUJyUO7eNubXyHLKOZfBG0KZw1Hogar7s5EjckkrHEvR9Ii+/nme0RG0VuNdcMM3TU +xe7pGR1byx9vyAq9YT68MCrAIYF2Uj44wOymaOeYvSn2vfQelM9q5vwdeJMRnPfzSJy pYdmco+/OhYo1C7SkipQCwllWqmiIubQ2TSf5H6nSQGj3MXBB7sy68Vj1K19SlxSmSjM Pp7Q== X-Gm-Message-State: AAQBX9fgF5mKvvixa0mN8A2qHGlcVdVU2CSAE5E9CYBjZ54+etFsZFhQ 48Ck3XuT3ONSAA7AV2ZlQSdXBA== X-Google-Smtp-Source: AKy350YG9Io2cuPjBGJzoLEha52jHD5Sn7O2C3Q9zxqK89nTaY5x5JTj0Z3JaKzFGgqQIJ2Qhpd19Q== X-Received: by 2002:a05:6a00:178b:b0:63a:fb40:891a with SMTP id s11-20020a056a00178b00b0063afb40891amr34556424pfg.2.1682546378528; Wed, 26 Apr 2023 14:59:38 -0700 (PDT) Received: from [10.0.17.156] ([50.221.140.188]) by smtp.gmail.com with ESMTPSA id o76-20020a62cd4f000000b0063d6666ee4csm11744264pfg.34.2023.04.26.14.59.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Apr 2023 14:59:38 -0700 (PDT) Content-Type: multipart/alternative; boundary="------------H4TXQ70nFa0YpRmmcKBz3cke" Message-ID: Date: Wed, 26 Apr 2023 14:59:37 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH v2] RISC-V: Fix sync.md and riscv.cc whitespace errors Content-Language: en-US To: Bernhard Reutner-Fischer , gcc-patches@gcc.gnu.org Cc: jeffreyalaw@gmail.com, schwab@linux-m68k.org References: <20230426205349.1131469-1-patrick@rivosinc.com> <20230426212106.1134636-1-patrick@rivosinc.com> <4BB13BEC-424F-43D2-AA55-41FA6E7E9D28@gmail.com> From: Patrick O'Neill In-Reply-To: <4BB13BEC-424F-43D2-AA55-41FA6E7E9D28@gmail.com> X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,MEDICAL_SUBJECT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------H4TXQ70nFa0YpRmmcKBz3cke Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/26/23 14:45, Bernhard Reutner-Fischer wrote: > On 26 April 2023 23:21:06 CEST, Patrick O'Neill wrote: >> This patch fixes whitespace errors introduced with >> https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html >> >> 2023-04-26 Patrick O'Neill >> >> gcc/ChangeLog: >> >> * config/riscv/riscv.cc: Fix whitespace. >> * config/riscv/sync.md: Fix whitespace. > The .md change above is gone by now. There are still some sync.md changes (comment whitespace/function whitespace changes). > No reason to resend the patch, just fixing it before you push it is fine, once ACKed (although such patches usually counts as obvious). Thanks for the help with this - still getting the hang of pushing my own changes! Patrick > Many thanks for the quick tweak! > cheers, > >> Signed-off-by: Patrick O'Neill >> --- >> Patch was checked with contrib/check_GNU_style.py >> >> Whitespace changes in this patch are 2 flavors: >> * Add space between function name and () >> * 2 spaces between end of comment and */ >> --- >> v2 Changelog: >> * Ignored checker warning for space before [] in rtl >> --- >> gcc/config/riscv/riscv.cc | 6 +++--- >> gcc/config/riscv/sync.md | 16 ++++++++-------- >> 2 files changed, 11 insertions(+), 11 deletions(-) >> >> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc >> index 0f890469d7a..1529855a2b4 100644 >> --- a/gcc/config/riscv/riscv.cc >> +++ b/gcc/config/riscv/riscv.cc >> @@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx *shift, rtx *mask, >> emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask, >> gen_lowpart (QImode, *shift))); >> >> - emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask)); >> + emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask)); >> } >> >> /* Leftshift a subword within an SImode register. */ >> @@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx shift, >> emit_move_insn (value_reg, simplify_gen_subreg (SImode, value, >> mode, 0)); >> >> - emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, >> - gen_lowpart (QImode, shift))); >> + emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg, >> + gen_lowpart (QImode, shift))); >> } >> >> /* Initialize the GCC target structure. */ >> diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md >> index 83be6431cb6..19274528262 100644 >> --- a/gcc/config/riscv/sync.md >> +++ b/gcc/config/riscv/sync.md >> @@ -128,10 +128,10 @@ >> { >> /* We have no QImode/HImode atomics, so form a mask, then use >> subword_atomic_fetch_strong_nand to implement a LR/SC version of the >> - operation. */ >> + operation. */ >> >> /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining >> - is disabled */ >> + is disabled. */ >> >> rtx old = gen_reg_rtx (SImode); >> rtx mem = operands[1]; >> @@ -193,10 +193,10 @@ >> { >> /* We have no QImode/HImode atomics, so form a mask, then use >> subword_atomic_fetch_strong_ to implement a LR/SC version of the >> - operation. */ >> + operation. */ >> >> /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining >> - is disabled */ >> + is disabled. */ >> >> rtx old = gen_reg_rtx (SImode); >> rtx mem = operands[1]; >> @@ -367,7 +367,7 @@ >> { >> rtx difference = gen_rtx_MINUS (SImode, val, exp); >> compare = gen_reg_rtx (SImode); >> - emit_move_insn (compare, difference); >> + emit_move_insn (compare, difference); >> } >> >> if (word_mode != SImode) >> @@ -393,10 +393,10 @@ >> { >> /* We have no QImode/HImode atomics, so form a mask, then use >> subword_atomic_cas_strong to implement a LR/SC version of the >> - operation. */ >> + operation. */ >> >> /* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining >> - is disabled */ >> + is disabled. */ >> >> rtx old = gen_reg_rtx (SImode); >> rtx mem = operands[1]; >> @@ -461,7 +461,7 @@ >> "TARGET_ATOMIC" >> { >> /* We have no QImode atomics, so use the address LSBs to form a mask, >> - then use an aligned SImode atomic. */ >> + then use an aligned SImode atomic. */ >> rtx result = operands[0]; >> rtx mem = operands[1]; >> rtx model = operands[2]; >> -- >> 2.34.1 >> --------------H4TXQ70nFa0YpRmmcKBz3cke--