[PATCH] mips: msa: truncate immediate shift amount [PR101922]

[PATCH] mips: msa: truncate immediate shift amount [PR101922]

[Xi Ruoyao]

When -mloongson-mmi is enabled, SHIFT_COUNT_TRUNCATED is turned off.
This causes untruncated immediate shift amount outputed into the asm,
and the GNU assembler refuses to assemble it.

Truncate immediate shift amount when outputing the asm instruction to
make GAS happy again.

gcc/

	PR target/101922
	* config/mips/mips-protos.h (mips_msa_output_shift_immediate):
	  Declare.
	* config/mips/mips.c (mips_msa_output_shift_immediate): New
	  function.
	* config/mips/mips-msa.md (vashl<mode>3, vashr<mode>3,
	  vlshr<mode>3): Call it.

gcc/testsuite/

	PR target/101922
	* gcc.target/mips/pr101922.c: New test.
---
 gcc/config/mips/mips-msa.md              | 27 ++++++++++++++++--------
 gcc/config/mips/mips-protos.h            |  1 +
 gcc/config/mips/mips.c                   | 21 ++++++++++++++++++
 gcc/testsuite/gcc.target/mips/pr101922.c | 19 +++++++++++++++++
 4 files changed, 59 insertions(+), 9 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/mips/pr101922.c

diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md
index 3a67f25be56..d3b27d132ad 100644
--- a/gcc/config/mips/mips-msa.md
+++ b/gcc/config/mips/mips-msa.md
@@ -870,9 +870,12 @@ (define_insn "vlshr<mode>3"
 	  (match_operand:IMSA 1 "register_operand" "f,f")
 	  (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
   "ISA_HAS_MSA"
-  "@
-   srl.<msafmt>\t%w0,%w1,%w2
-   srli.<msafmt>\t%w0,%w1,%E2"
+{
+  if (which_alternative == 0)
+    return "srl.<msafmt>\t%w0,%w1,%w2";
+
+  return mips_msa_output_shift_immediate("srli.<msafmt>\t%w0,%w1,%E2", operands);
+}
   [(set_attr "type" "simd_shift")
    (set_attr "mode" "<MODE>")])
 
@@ -882,9 +885,12 @@ (define_insn "vashr<mode>3"
 	  (match_operand:IMSA 1 "register_operand" "f,f")
 	  (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
   "ISA_HAS_MSA"
-  "@
-   sra.<msafmt>\t%w0,%w1,%w2
-   srai.<msafmt>\t%w0,%w1,%E2"
+{
+  if (which_alternative == 0)
+    return "sra.<msafmt>\t%w0,%w1,%w2";
+
+  return mips_msa_output_shift_immediate("srai.<msafmt>\t%w0,%w1,%E2", operands);
+}
   [(set_attr "type" "simd_shift")
    (set_attr "mode" "<MODE>")])
 
@@ -894,9 +900,12 @@ (define_insn "vashl<mode>3"
 	  (match_operand:IMSA 1 "register_operand" "f,f")
 	  (match_operand:IMSA 2 "reg_or_vector_same_uimm6_operand" "f,Uuv6")))]
   "ISA_HAS_MSA"
-  "@
-   sll.<msafmt>\t%w0,%w1,%w2
-   slli.<msafmt>\t%w0,%w1,%E2"
+{
+  if (which_alternative == 0)
+    return "sll.<msafmt>\t%w0,%w1,%w2";
+
+  return mips_msa_output_shift_immediate("slli.<msafmt>\t%w0,%w1,%E2", operands);
+}
   [(set_attr "type" "simd_shift")
    (set_attr "mode" "<MODE>")])
 
diff --git a/gcc/config/mips/mips-protos.h b/gcc/config/mips/mips-protos.h
index a5e4151b9e6..8d97eb36125 100644
--- a/gcc/config/mips/mips-protos.h
+++ b/gcc/config/mips/mips-protos.h
@@ -317,6 +317,7 @@ extern const char *mips_output_sync_loop (rtx_insn *, rtx *);
 extern unsigned int mips_sync_loop_insns (rtx_insn *, rtx *);
 extern const char *mips_output_division (const char *, rtx *);
 extern const char *mips_msa_output_division (const char *, rtx *);
+extern const char *mips_msa_output_shift_immediate (const char *, rtx *);
 extern const char *mips_output_probe_stack_range (rtx, rtx);
 extern bool mips_hard_regno_rename_ok (unsigned int, unsigned int);
 extern bool mips_linked_madd_p (rtx_insn *, rtx_insn *);
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 89d1be6cea6..3d5be369b1c 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -14495,6 +14495,27 @@ mips_msa_output_division (const char *division, rtx *operands)
     }
   return s;
 }
+
+/* Return the assembly code for MSA immediate shift instructions,
+   which has the operands given by OPERANDS.  Truncate the shift amount
+   to make GAS happy.  */
+
+const char *
+mips_msa_output_shift_immediate (const char *shift, rtx *operands)
+{
+  rtx amount = operands[2];
+  machine_mode mode = amount->mode;
+
+  unsigned val = UINTVAL (CONST_VECTOR_ELT (amount, 0));
+  val &= GET_MODE_UNIT_BITSIZE (mode) - 1;
+  if (!val)
+    return "";
+
+  rtx c = gen_int_mode (val, GET_MODE_INNER (mode));
+  operands[2] = gen_const_vec_duplicate (mode, c);
+
+  return shift;
+}
 \f
 /* Return true if destination of IN_INSN is used as add source in
    OUT_INSN. Both IN_INSN and OUT_INSN are of type fmadd. Example:
diff --git a/gcc/testsuite/gcc.target/mips/pr101922.c b/gcc/testsuite/gcc.target/mips/pr101922.c
new file mode 100644
index 00000000000..00a6e495ba2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/mips/pr101922.c
@@ -0,0 +1,19 @@
+/* PR target/101922
+   This was triggering an assembler error with -O3 -mmsa -mloongson-mmi. */
+
+/* { dg-do assemble } */
+/* { dg-options "-mmsa -mloongson-mmi" } */
+
+typedef __INT8_TYPE__ i8;
+typedef __INT32_TYPE__ i32;
+
+i8 d[16];
+
+i32 f(i32 x) {
+  int i;
+  for (i = 0; i < 16; i++) {
+    i32 t = (i32) d[i] >> 31;
+    x &= t;
+  }
+  return x;
+}
-- 
2.33.0

Re: [PATCH] mips: msa: truncate immediate shift amount [PR101922]

[Xi Ruoyao]

On Sat, 2021-08-21 at 01:07 +0800, Xi Ruoyao via Gcc-patches wrote:
> When -mloongson-mmi is enabled, SHIFT_COUNT_TRUNCATED is turned off.
> This causes untruncated immediate shift amount outputed into the asm,
> and the GNU assembler refuses to assemble it.
> 
> Truncate immediate shift amount when outputing the asm instruction to
> make GAS happy again.
> 
> gcc/
> 
>         PR target/101922
>         * config/mips/mips-protos.h (mips_msa_output_shift_immediate):
>           Declare.
>         * config/mips/mips.c (mips_msa_output_shift_immediate): New
>           function.
>         * config/mips/mips-msa.md (vashl<mode>3, vashr<mode>3,
>           vlshr<mode>3): Call it.
> 
> gcc/testsuite/
> 
>         PR target/101922
>         * gcc.target/mips/pr101922.c: New test.

Forgot to mention: tested on mips64el-linux-gnu, OK for trunk?

Re: [PATCH] mips: msa: truncate immediate shift amount [PR101922]

[Jeff Law]

On 8/20/2021 11:07 AM, Xi Ruoyao via Gcc-patches wrote:
> When -mloongson-mmi is enabled, SHIFT_COUNT_TRUNCATED is turned off.
> This causes untruncated immediate shift amount outputed into the asm,
> and the GNU assembler refuses to assemble it.
>
> Truncate immediate shift amount when outputing the asm instruction to
> make GAS happy again.
>
> gcc/
>
> 	PR target/101922
> 	* config/mips/mips-protos.h (mips_msa_output_shift_immediate):
> 	  Declare.
> 	* config/mips/mips.c (mips_msa_output_shift_immediate): New
> 	  function.
> 	* config/mips/mips-msa.md (vashl<mode>3, vashr<mode>3,
> 	  vlshr<mode>3): Call it.
>
> gcc/testsuite/
>
> 	PR target/101922
> 	* gcc.target/mips/pr101922.c: New test.
OK.

Q. Looking out further, is it going to continue to make sense to have 
loongson continue to be based on the mips port, or is it going to make 
more sense to have a distinct loongson port?

Jeff

Re: [PATCH] mips: msa: truncate immediate shift amount [PR101922]

[Xi Ruoyao]

On Sun, 2021-08-22 at 19:21 -0600, Jeff Law wrote:
> 
> 
> On 8/20/2021 11:07 AM, Xi Ruoyao via Gcc-patches wrote:
> > When -mloongson-mmi is enabled, SHIFT_COUNT_TRUNCATED is turned off.
> > This causes untruncated immediate shift amount outputed into the
> > asm,
> > and the GNU assembler refuses to assemble it.
> > 
> > Truncate immediate shift amount when outputing the asm instruction
> > to
> > make GAS happy again.
> > 
> > gcc/
> > 
> >         PR target/101922
> >         * config/mips/mips-protos.h
> > (mips_msa_output_shift_immediate):
> >           Declare.
> >         * config/mips/mips.c (mips_msa_output_shift_immediate): New
> >           function.
> >         * config/mips/mips-msa.md (vashl<mode>3, vashr<mode>3,
> >           vlshr<mode>3): Call it.
> > 
> > gcc/testsuite/
> > 
> >         PR target/101922
> >         * gcc.target/mips/pr101922.c: New test.
> OK.

Committed @ f93f0868919.

> Q. Looking out further, is it going to continue to make sense to have 
> more sense to have a distinct loongson port?

The latest Loongson processors (branded Loongson 3A5000 for desktop,
3B5000 for workstation and server, and 3C5000L for server) have moved
away from MIPS to a new RISC architecture named "LoongArch".  Its design
learnt some traits from MIPSr6 and RISC-V I think, but it's not a simple
MIPS variant and will need a new port for GCC.  A manual of LoongArch
basic instructions is at
https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html.
LoongArch also have 128 and 256 bit vector insturctions, but the manual
is not published yet.

A team from Loongson is working on the port, the (experimental) source
code is available at
https://github.com/loongson/gcc/commits/loongarch-12.  It's not ready
for upstream reviewing yet.

For "legacy" Loongson processors using MIPS, I suggest to keep the
support as a MIPS extension.  I'll try to keep it in an "usable" state
(i. e. fix, or at least workaround ICE and bad assemble code like this).
If one day we can't maintain it anymore we'd have to sadly deprecate and
remove Loongson MMI support.
-- 
Xi Ruoyao <xry111@mengyan1223.wang>
School of Aerospace Science and Technology, Xidian University