From: Tobias Burnus <tobias@codesourcery.com>
To: Andrew Stubbs <ams@codesourcery.com>,
gcc-patches <gcc-patches@gcc.gnu.org>
Subject: Re: [Patch] gcn: Add __builtin_gcn_{get_stack_limit,first_call_this_thread_p}
Date: Sat, 19 Nov 2022 11:46:32 +0100 [thread overview]
Message-ID: <d6f80343-3b75-e1a5-8773-f8d30bdf16c0@codesourcery.com> (raw)
In-Reply-To: <fbcfe3a7-1275-4906-f576-03695605f603@codesourcery.com>
On 18.11.22 18:49, Andrew Stubbs wrote:
> On 18/11/2022 17:20, Tobias Burnus wrote:
>
> This looks wrong:
>
>> + /* stackbase = (stack_segment_decr & 0x0000ffffffffffff)
>> + + stack_wave_offset);
>> + seg_size = dispatch_ptr->private_segment_size;
>> + stacklimit = stackbase + seg_size*64;
(this should be '*seg_size' not 'seg_size' and the name should be
s/seg_size/seg_size_ptr/.)
>> + with segsize = dispatch_ptr + 6*sizeof(int16_t) +
>> 3*sizeof(int32_t);
>> + cf. struct hsa_kernel_dispatch_packet_s in the HSA doc. */
>> + rtx ptr;
>> + if (cfun->machine->args.reg[DISPATCH_PTR_ARG] >= 0
>> + && cfun->machine->args.reg[PRIVATE_SEGMENT_BUFFER_ARG] >= 0)
>> + {
>> + rtx size_rtx = gen_rtx_REG (DImode,
>> + cfun->machine->args.reg[DISPATCH_PTR_ARG]);
>> + size_rtx = gen_rtx_MEM (DImode,
>> + gen_rtx_PLUS (DImode, size_rtx,
>> + GEN_INT (6*16 + 3*32)));
>> + size_rtx = gen_rtx_MULT (DImode, size_rtx, GEN_INT (64));
>> +
(Reading it, I think it should be '..._MEM(SImode,' and
'..._MULT(SImode' instead of DImode.)
> seg_size is calculated from the private_segment_size loaded from the
> dispatch_ptr, not calculated from the dispatch_ptr itself.
Isn't this what thee code tries to do? Namely:
My understanding is that
dispatch_ptr->private_segment_size == *((char*)dispatch_ptr + 192)
And the latter is what I attempt to do. I have a very limited knowledge
of insn/rtx/RTL and of GCN assemply; thus, I likely have done something
stupid. Having said this, Here is what I get:
(Where asm("s4") == dispatch_ptr)
s_add_u32 s2, s4, 192
s_addc_u32 s3, s5, 0
v_writelane_b32 v4, s2, 0
v_writelane_b32 v5, s3, 0
s_mov_b64 exec, 1
flat_load_dwordx2 v[4:5], v[4:5]
s_waitcnt 0
v_lshlrev_b64 v[4:5], 6, v[4:5]
v_readlane_b32 s2, v4, 0
v_readlane_b32 s3, v5, 0
Not that I really understand every line, but at a glance it
looks okay.
The 192 is because of (quoting newlib/libc/machine/amdgcn/getreent.c):
typedef struct hsa_kernel_dispatch_packet_s {
uint16_t header ;
uint16_t setup;
uint16_t workgroup_size_x ;
uint16_t workgroup_size_y ;
uint16_t workgroup_size_z;
uint16_t reserved0;
uint32_t grid_size_x ;
uint32_t grid_size_y ;
uint32_t grid_size_z;
uint32_t private_segment_size;
i.e. 6*16 + 3*32 = 192 – and we want to read a 32bit unsigned int.
* * *
Admittedly, there is probably something not quite right as I see with gfx908
# of expected passes 27476
# of unexpected failures 317
where 317 FAIL comes from 88 testcase files.
That's not a a very high number but more than the usual fails, which shows that
something is not quite right.
* * *
I am pretty sure that I missed something - but the question is what.
I hope you can help me pinpoint the place where it goes wrong.
Thanks,
Tobias
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next prev parent reply other threads:[~2022-11-19 10:46 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-18 17:20 Tobias Burnus
2022-11-18 17:49 ` Andrew Stubbs
2022-11-19 10:46 ` Tobias Burnus [this message]
2022-11-20 0:23 ` Andrew Stubbs
2022-11-21 13:41 ` Tobias Burnus
2022-11-21 14:58 ` Stubbs, Andrew
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