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To: gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn References: <20230407083820.752753-1-chenglulu@loongson.cn> From: Lulu Cheng Message-ID: Date: Tue, 18 Apr 2023 10:02:56 +0800 User-Agent: Mozilla/5.0 (X11; Linux mips64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20230407083820.752753-1-chenglulu@loongson.cn> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8Bx57xQ+j1kPAQsAA--.50235S2 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBjvJXoW3Ar13JF4fKF4rtrW7uF47CFg_yoWxCF43pr 4Ikw1ayrW0qr129ryfArZ5XF9aqFs7Ww12yF43GryxCF45Jr9av3yakrZxAFs8K34kuF1I v3y7J34q9an8AaDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bxkYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UM2AI xVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r126r1DMcIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07AlzVAYIcxG8wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU82g43UUUUU== X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_PASS,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Pushed to r14-14. ÔÚ 2023/4/7 ÏÂÎç4:38, Lulu Cheng дµÀ: > gcc/ChangeLog: > > * doc/extend.texi: Add section for LoongArch Base Built-in functions. > --- > gcc/doc/extend.texi | 129 ++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 129 insertions(+) > > --- > v1 -> v2: > (1) Does not use i8, u8, i16, u16 etc. > (2) Add the description information of the built-in functions before encapsulation. > > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 3adb67aa47a..9fbb33b370b 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -14669,6 +14669,7 @@ instructions, but allow the compiler to schedule those calls. > * Blackfin Built-in Functions:: > * BPF Built-in Functions:: > * FR-V Built-in Functions:: > +* LoongArch Base Built-in Functions:: > * MIPS DSP Built-in Functions:: > * MIPS Paired-Single Support:: > * MIPS Loongson Built-in Functions:: > @@ -16197,6 +16198,134 @@ Use the @code{nldub} instruction to load the contents of address @var{x} > into the data cache. The instruction is issued in slot I1@. > @end table > > +@node LoongArch Base Built-in Functions > +@subsection LoongArch Base Built-in Functions > + > +These built-in functions are available for LoongArch. > + > +Data Type Description: > +@itemize > +@item @code{imm0_31}, a compile-time constant in range 0 to 31; > +@item @code{imm0_16383}, a compile-time constant in range 0 to 16383; > +@item @code{imm0_32767}, a compile-time constant in range 0 to 32767; > +@item @code{imm_n2048_2047}, a compile-time constant in range -2048 to 2047; > +@end itemize > + > +The intrinsics provided are listed below: > +@smallexample > + unsigned int __builtin_loongarch_movfcsr2gr (imm0_31) > + void __builtin_loongarch_movgr2fcsr (imm0_31, unsigned int) > + void __builtin_loongarch_cacop_d (imm0_31, unsigned long int, imm_n2048_2047) > + unsigned int __builtin_loongarch_cpucfg (unsigned int) > + void __builtin_loongarch_asrtle_d (long int, long int) > + void __builtin_loongarch_asrtgt_d (long int, long int) > + long int __builtin_loongarch_lddir_d (long int, imm0_31) > + void __builtin_loongarch_ldpte_d (long int, imm0_31) > + > + int __builtin_loongarch_crc_w_b_w (char, int) > + int __builtin_loongarch_crc_w_h_w (short, int) > + int __builtin_loongarch_crc_w_w_w (int, int) > + int __builtin_loongarch_crc_w_d_w (long int, int) > + int __builtin_loongarch_crcc_w_b_w (char, int) > + int __builtin_loongarch_crcc_w_h_w (short, int) > + int __builtin_loongarch_crcc_w_w_w (int, int) > + int __builtin_loongarch_crcc_w_d_w (long int, int) > + > + unsigned int __builtin_loongarch_csrrd_w (imm0_16383) > + unsigned int __builtin_loongarch_csrwr_w (unsigned int, imm0_16383) > + unsigned int __builtin_loongarch_csrxchg_w (unsigned int, unsigned int, imm0_16383) > + unsigned long int __builtin_loongarch_csrrd_d (imm0_16383) > + unsigned long int __builtin_loongarch_csrwr_d (unsigned long int, imm0_16383) > + unsigned long int __builtin_loongarch_csrxchg_d (unsigned long int, unsigned long int, imm0_16383) > + > + unsigned char __builtin_loongarch_iocsrrd_b (unsigned int) > + unsigned short __builtin_loongarch_iocsrrd_h (unsigned int) > + unsigned int __builtin_loongarch_iocsrrd_w (unsigned int) > + unsigned long int __builtin_loongarch_iocsrrd_d (unsigned int) > + void __builtin_loongarch_iocsrwr_b (unsigned char, unsigned int) > + void __builtin_loongarch_iocsrwr_h (unsigned short, unsigned int) > + void __builtin_loongarch_iocsrwr_w (unsigned int, unsigned int) > + void __builtin_loongarch_iocsrwr_d (unsigned long int, unsigned int) > + > + void __builtin_loongarch_dbar (imm0_32767) > + void __builtin_loongarch_ibar (imm0_32767) > + > + void __builtin_loongarch_syscall (imm0_32767) > + void __builtin_loongarch_break (imm0_32767) > +@end smallexample > + > +@emph{Note:}Since the control register is divided into 32-bit and 64-bit, > +but the access instruction is not distinguished. So GCC renames the control > +instructions when implementing intrinsics. > + > +Take the csrrd instruction as an example, built-in functions are implemented as follows: > +@smallexample > + __builtin_loongarch_csrrd_w // When reading the 32-bit control register use. > + __builtin_loongarch_csrrd_d // When reading the 64-bit control register use. > +@end smallexample > + > +For the convenience of use, the built-in functions are encapsulated, > +the encapsulated functions and @code{__drdtime_t, __rdtime_t} are > +defined in the @code{larchintrin.h}. So if you call the following > +function you need to include @code{larchintrin.h}. > + > +@smallexample > + typedef struct drdtime@{ > + unsigned long dvalue; > + unsigned long dtimeid; > + @} __drdtime_t; > + > + typedef struct rdtime@{ > + unsigned int value; > + unsigned int timeid; > + @} __rdtime_t; > +@end smallexample > + > +@smallexample > + __drdtime_t __rdtime_d (void) > + __rdtime_t __rdtimel_w (void) > + __rdtime_t __rdtimeh_w (void) > + unsigned int __movfcsr2gr (imm0_31) > + void __movgr2fcsr (imm0_31, unsigned int) > + void __cacop_d (imm0_31, unsigned long, imm_n2048_2047) > + unsigned int __cpucfg (unsigned int) > + void __asrtle_d (long int, long int) > + void __asrtgt_d (long int, long int) > + long int __lddir_d (long int, imm0_31) > + void __ldpte_d (long int, imm0_31) > + > + int __crc_w_b_w (char, int) > + int __crc_w_h_w (short, int) > + int __crc_w_w_w (int, int) > + int __crc_w_d_w (long int, int) > + int __crcc_w_b_w (char, int) > + int __crcc_w_h_w (short, int) > + int __crcc_w_w_w (int, int) > + int __crcc_w_d_w (long int, int) > + > + unsigned int __csrrd_w (imm0_16383) > + unsigned int __csrwr_w (unsigned int, imm0_16383) > + unsigned int __csrxchg_w (unsigned int, unsigned int, imm0_16383) > + unsigned long __csrrd_d (imm0_16383) > + unsigned long __csrwr_d (unsigned long, imm0_16383) > + unsigned long __csrxchg_d (unsigned long, unsigned long, imm0_16383) > + > + unsigned char __iocsrrd_b (unsigned int) > + unsigned short __iocsrrd_h (unsigned int) > + unsigned int __iocsrrd_w (unsigned int) > + unsigned long __iocsrrd_d (unsigned int) > + void __iocsrwr_b (unsigned char, unsigned int) > + void __iocsrwr_h (unsigned short, unsigned int) > + void __iocsrwr_w (unsigned int, unsigned int) > + void __iocsrwr_d (unsigned long, unsigned int) > + > + void __dbar (imm0_32767) > + void __ibar (imm0_32767) > + > + void __syscall (imm0_32767) > + void __break (imm0_32767) > +@end smallexample > + > @node MIPS DSP Built-in Functions > @subsection MIPS DSP Built-in Functions >