From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 71651 invoked by alias); 5 Sep 2017 09:04:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 71635 invoked by uid 89); 5 Sep 2017 09:04:27 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=irregularity, Best X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 05 Sep 2017 09:04:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B24D13D5; Tue, 5 Sep 2017 02:04:19 -0700 (PDT) Received: from [10.2.206.52] (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2ED6D3F578; Tue, 5 Sep 2017 02:04:18 -0700 (PDT) Subject: Re: [PATCH, GCC/testsuite/ARM, ping3] Fix coprocessor intrinsic test failures on ARMv8-A From: Thomas Preudhomme To: Kyrill Tkachov , Ramana Radhakrishnan , Richard Earnshaw , "gcc-patches@gcc.gnu.org" References: <4ab8c299-8b7e-6baf-d3ca-6021c0888ba8@foss.arm.com> Message-ID: Date: Tue, 05 Sep 2017 09:04:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/mixed; boundary="------------661EB80C28D63EC6F45E5A7B" X-IsSubscribed: yes X-SW-Source: 2017-09/txt/msg00227.txt.bz2 This is a multi-part message in MIME format. --------------661EB80C28D63EC6F45E5A7B Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Content-length: 2965 Ping? Best regards, Thomas On 23/08/17 11:59, Thomas Preudhomme wrote: > Ping? > > Best regards, > > Thomas > > On 17/07/17 09:51, Thomas Preudhomme wrote: >> Ping? >> >> Best regards, >> >> Thomas >> >> On 12/07/17 14:31, Thomas Preudhomme wrote: >>> Coprocessor intrinsic tests in gcc.target/arm/acle test whether >>> __ARM_FEATURE_COPROC has the right bit defined before calling the >>> intrinsic. This allows to test both the correct setting of that macro >>> and the availability and correct working of the intrinsic. However the >>> __ARM_FEATURE_COPROC macro is no longer defined for ARMv8-A since >>> r249399. >>> >>> This patch changes the testcases to skip that test for ARMv8-A and >>> ARMv8-R targets. It also fixes some irregularity in the coprocessor >>> effective targets: >>> - add ldcl and stcl to the list of instructions listed as guarded by >>> arm_coproc1_ok >>> - enable tests guarded by arm_coproc2_ok, arm_coproc3_ok and >>> arm_coproc4_ok for Thumb-2 capable targets but disable for Thumb-1 >>> targets. >>> >>> ChangeLog entry is as follows: >>> >>> *** gcc/testsuite/ChangeLog *** >>> >>> 2017-07-04 Thomas Preud'homme >>> >>> * gcc.target/arm/acle/cdp.c: Skip __ARM_FEATURE_COPROC check for >>> ARMv8-A and ARMv8-R. >>> * gcc.target/arm/acle/cdp2.c: Likewise. >>> * gcc.target/arm/acle/ldc.c: Likewise. >>> * gcc.target/arm/acle/ldc2.c: Likewise. >>> * gcc.target/arm/acle/ldc2l.c: Likewise. >>> * gcc.target/arm/acle/ldcl.c: Likewise. >>> * gcc.target/arm/acle/mcr.c: Likewise. >>> * gcc.target/arm/acle/mcr2.c: Likewise. >>> * gcc.target/arm/acle/mcrr.c: Likewise. >>> * gcc.target/arm/acle/mcrr2.c: Likewise. >>> * gcc.target/arm/acle/mrc.c: Likewise. >>> * gcc.target/arm/acle/mrc2.c: Likewise. >>> * gcc.target/arm/acle/mrrc.c: Likewise. >>> * gcc.target/arm/acle/mrrc2.c: Likewise. >>> * gcc.target/arm/acle/stc.c: Likewise. >>> * gcc.target/arm/acle/stc2.c: Likewise. >>> * gcc.target/arm/acle/stc2l.c: Likewise. >>> * gcc.target/arm/acle/stcl.c: Likewise. >>> * lib/target-supports.exp: >>> (check_effective_target_arm_coproc1_ok_nocache): Mention ldcl >>> and stcl in the comment. >>> (check_effective_target_arm_coproc2_ok_nocache): Allow Thumb-2 targets >>> and disable Thumb-1 targets. >>> (check_effective_target_arm_coproc3_ok_nocache): Likewise. >>> (check_effective_target_arm_coproc4_ok_nocache): Likewise. >>> >>> Tested by running all tests in gcc.target/arm/acle before and after this >>> patch for ARMv6-M, ARMv7-M, ARMv7E-M, ARMv3, ARMv4 (ARM state), ARMv4T >>> (Thumb state), ARMv5 (ARM state), ARMv5TE (ARM state), ARMv6 (ARM >>> state), ARMv6T2 (Thumb state) and and ARMv8-A (both state). The only >>> changes are for ARMv8-A where tests FAILing are now PASSing again. >>> >>> Is this ok for trunk? >>> >>> Best regards, >>> >>> Thomas --------------661EB80C28D63EC6F45E5A7B Content-Type: text/x-patch; name="fix_coproc_testcase_failure.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="fix_coproc_testcase_failure.patch" Content-length: 12385 diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp.c b/gcc/testsuite/gcc.target/arm/acle/cdp.c index cebd8c4024ea1930f490f63e5267a33bac59a3a8..cfa922a797cddbf4a99f27ec156fd2d2fc9a460d 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cdp.c +++ b/gcc/testsuite/gcc.target/arm/acle/cdp.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/cdp2.c b/gcc/testsuite/gcc.target/arm/acle/cdp2.c index 945d435d2fb99962ff47d921d9cb3633cb75bb79..b18076c26274043be8ac71e6516b9b6eac3b4137 100644 --- a/gcc/testsuite/gcc.target/arm/acle/cdp2.c +++ b/gcc/testsuite/gcc.target/arm/acle/cdp2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc.c b/gcc/testsuite/gcc.target/arm/acle/ldc.c index cd57343208fc5b17e5391d11d126d20e224d6566..10c879f4a15e7c293541c61dc974d972798ecedf 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2.c b/gcc/testsuite/gcc.target/arm/acle/ldc2.c index d7691e30d763d1e921817fd586b47888e1b5c78f..d561adacccf358a1dbfa9db253c9bc08847c7e33 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c index 9ee63afa05501c6d2412df679d50b202aef4529b..2c2a381c272e3f6f5c5a1335a80c49089e6b1fb2 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldc2l.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldc2l.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/ldcl.c b/gcc/testsuite/gcc.target/arm/acle/ldcl.c index a6bfd9011dc2c714ad7f30378f95c2c4ec74ffe7..acbe5a3a2d0ce709b0d5a874428e8a210f21465c 100644 --- a/gcc/testsuite/gcc.target/arm/acle/ldcl.c +++ b/gcc/testsuite/gcc.target/arm/acle/ldcl.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr.c b/gcc/testsuite/gcc.target/arm/acle/mcr.c index 7095dcbc3ad13efd6a15a4a0cc3ea8ece4d910a3..fb8e3c28ea1e8a7274fdfaabbb045b991953bfb4 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcr.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mcr2.c b/gcc/testsuite/gcc.target/arm/acle/mcr2.c index 2a4b0ce45593c3d88635a9f796f15ae115108d40..b83d9d7df8b5c87c0ae1a5a8d482eb6f5e0e696f 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcr2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr.c b/gcc/testsuite/gcc.target/arm/acle/mcrr.c index bcfbe1a4855e95a878d91a8e45a197d96eb8fea8..468dd96fb9b6a726aaa235172340a904b4e420d8 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc3_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x4) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x4) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c index afd07e67f215e2bbb0e65eb9fdb64c5b865bbda7..1173ad06b533233651bddb1dd9d118ddeed5f8ae 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mcrr2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mcrr2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc4_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x8) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x8) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc.c b/gcc/testsuite/gcc.target/arm/acle/mrc.c index 809b6c9c2652806053786a8104df188f5f1f59bf..b09634f14f2db4d85f21e516b9f13909dc735eb9 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrc.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrc2.c index 4c06ea39b37ab529241ec1a99032471a0fac3de1..7dd691f0e49bab722a685075e638a4227a7239e8 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrc2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc.c b/gcc/testsuite/gcc.target/arm/acle/mrrc.c index 802de083d5cef277b1c3b7e674754efcfc02e91d..c004660fadcadb912b3c246241843e22242dffcc 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc3_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x4) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x4) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c index adf39563e293b917d9c5defc289448c45e731f05..b5d56da8f90b2397408617dda610703f44f4435b 100644 --- a/gcc/testsuite/gcc.target/arm/acle/mrrc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/mrrc2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc4_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x8) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x8) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/stc.c b/gcc/testsuite/gcc.target/arm/acle/stc.c index 2714f65787e0571117c4ace41bdc1376d3a2e1a0..6155bd07dc38e1435bbc1df737a9e727ac7a768b 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2.c b/gcc/testsuite/gcc.target/arm/acle/stc2.c index 0a84652e0f00c1691309b2fb108f29ced30f87d0..57598d986a36ada7988dba430f7ee9d11897b605 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc2.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc2.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/stc2l.c b/gcc/testsuite/gcc.target/arm/acle/stc2l.c index 2453d04ad72b10e51fec55f8d302d48f0b9c3c0d..0bca8dfa1f89bfe92221b63b63ebff0990a58021 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stc2l.c +++ b/gcc/testsuite/gcc.target/arm/acle/stc2l.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc2_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x2) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x2) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/gcc.target/arm/acle/stcl.c b/gcc/testsuite/gcc.target/arm/acle/stcl.c index affdaa27982947bafefad4dc57bd838c03aa3b64..be6270f26719f19167635d43f0ea02356369b16b 100644 --- a/gcc/testsuite/gcc.target/arm/acle/stcl.c +++ b/gcc/testsuite/gcc.target/arm/acle/stcl.c @@ -5,7 +5,8 @@ /* { dg-require-effective-target arm_coproc1_ok } */ #include "arm_acle.h" -#if (__ARM_FEATURE_COPROC & 0x1) == 0 +#if (__ARM_ARCH < 8 || !defined (__ARM_ARCH_ISA_ARM)) \ + && (__ARM_FEATURE_COPROC & 0x1) == 0 #error "__ARM_FEATURE_COPROC does not have correct feature bits set" #endif diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index f6e24401879429c2ef1a5dc9f50ff980eafcc1f3..9d67323eb800e8c0af154a2657203d6762b61473 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -8372,8 +8372,8 @@ proc check_effective_target_rdrand { } { } "-mrdrnd" ] } -# Return 1 if the target supports coprocessor instructions: cdp, ldc, stc, mcr and -# mrc. +# Return 1 if the target supports coprocessor instructions: cdp, ldc, ldcl, +# stc, stcl, mcr and mrc. proc check_effective_target_arm_coproc1_ok_nocache { } { if { ![istarget arm*-*-*] } { return 0 @@ -8398,7 +8398,7 @@ proc check_effective_target_arm_coproc2_ok_nocache { } { return 0 } return [check_no_compiler_messages_nocache arm_coproc2_ok assembly { - #if __ARM_ARCH < 5 + #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 5 #error FOO #endif }] @@ -8417,7 +8417,8 @@ proc check_effective_target_arm_coproc3_ok_nocache { } { return 0 } return [check_no_compiler_messages_nocache arm_coproc3_ok assembly { - #if __ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__) + #if (__thumb__ && !__thumb2__) \ + || (__ARM_ARCH < 6 && !defined (__ARM_ARCH_5TE__)) #error FOO #endif }] @@ -8436,7 +8437,7 @@ proc check_effective_target_arm_coproc4_ok_nocache { } { return 0 } return [check_no_compiler_messages_nocache arm_coproc4_ok assembly { - #if __ARM_ARCH < 6 + #if (__thumb__ && !__thumb2__) || __ARM_ARCH < 6 #error FOO #endif }] --------------661EB80C28D63EC6F45E5A7B--