From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 27E693858D3C for ; Sat, 23 Dec 2023 07:00:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 27E693858D3C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 27E693858D3C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703314853; cv=none; b=XSXXYmPB5uh8UslBx2KIRgRMgDe+SPbjrI5NdEZjJFoK5WsZOZVUASKrBdfkrc442csXgHLNYB6OMEz/WVpBgSoCyDoSNVoQArvovsm4UJCrnKS7DAq0by3FqkiPVanKFLhrn+4bOyQreXBeM1qF7zGTyRVjdEYpmjnOcDL3oQ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1703314853; c=relaxed/simple; bh=t9Vk06hiEaf8Dm4dKimavSAEAlMJp0w3xw7RudjIumU=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=ISFovbgKFOgvtQL3lNK4eGnX7O0prsCVhCQtHLfF+HUiknUzFKklV4M47Ubiiz2Ww288m5II+G7SSkwQrYxmsj1Rrs23rGq0TyGzQdFscnjrQoTa6DenQ02hUaSQRdK2caqAl+MvCB7zg0upikP/mXYa8wdP/GQ7sO9jMCzlTZY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rGw07-0005QK-IT for gcc-patches@gcc.gnu.org; Sat, 23 Dec 2023 02:00:50 -0500 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8AxJPCWhYZlEwoEAA--.20429S3; Sat, 23 Dec 2023 15:00:39 +0800 (CST) Received: from [10.20.4.107] (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxG+SShYZlsa4GAA--.30584S3; Sat, 23 Dec 2023 15:00:35 +0800 (CST) Subject: Re: [PATCH] LoongArch: Expand left rotate to right rotate with negated amount To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn, c@jia.je References: <20231218134414.1513666-1-xry111@xry111.site> From: chenglulu Message-ID: Date: Sat, 23 Dec 2023 15:00:34 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20231218134414.1513666-1-xry111@xry111.site> Content-Type: multipart/alternative; boundary="------------EAC82B37AF38AA1EA176071E" Content-Language: en-US X-CM-TRANSID:AQAAf8BxG+SShYZlsa4GAA--.30584S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3ArWrXF13ZF4fJrW3Cw43XFc_yoW7GFWfpr ZrZw15tF48JFs7Kwn7ta4aqa1aqrn7Gry7Zasag3s2kF17Xry8Z3Wrta9rXFy5Xa1Yqr1S vr4fua1jga1agwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ34c02F40En4AKxVAvwIkv4cxYr27v73VFW2AGmfu7bjvjm3AaLaJ3UjIY CTnIWjp_UUUYy7kC6x804xWl14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcI k0rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK 021l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r 1j6r4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j 6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc02F4 0En4AKxVAvwIkv4cxYr24lYx0E2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r4j 6F4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvEwIxGrwCjr7xvwVCIw2I0I7xG6c02F4 1lc7I2V7IY0VAS07AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r106r1rMI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_JF0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0x vEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVj vjDU0xZFpf9x07j1VbkUUUUU= Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -35 X-Spam_score: -3.6 X-Spam_bar: --- X-Spam_report: (-3.6 / 5.0 requ) BAYES_00=-1.9,HTML_MESSAGE=0.001,MIME_CHARSET_FARAWAY=2.45,NICE_REPLY_A=-4.121,SPF_HELO_NONE=0.001,SPF_PASS=-0.001,T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00,BODY_8BITS,GIT_PATCH_0,HTML_MESSAGE,KAM_DMARC_STATUS,KAM_SHORT,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_FAIL,SPF_HELO_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multi-part message in MIME format. --------------EAC82B37AF38AA1EA176071E Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Hi, This patch will cause the following tests to fail: +FAIL: gcc.dg/vect/pr97081-2.c (internal compiler error: in extract_insn, at recog.cc:2812) +FAIL: gcc.dg/vect/pr97081-2.c (test for excess errors) +FAIL: gcc.dg/vect/pr97081-2.c -flto -ffat-lto-objects (internal compiler error: in extract_insn, at recog.cc:2812) +FAIL: gcc.dg/vect/pr97081-2.c -flto -ffat-lto-objects (test for excess errors) ÔÚ 2023/12/18 ÏÂÎç9:43, Xi Ruoyao дµÀ: > gcc/ChangeLog: > > * config/loongarch/loongarch.md (rotl3): > New define_expand. > * config/loongarch/simd.md (vrotl3): Likewise. > (rotl3): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/rotl-with-rotr.c: New test. > * gcc.target/loongarch/rotl-with-vrotr.c: New test. > * gcc.target/loongarch/rotl-with-xvrotr.c: New test. > --- > > Bootstrapped and regtested on loongarch64-linux-gnu. Ok for trunk? > > gcc/config/loongarch/loongarch.md | 12 ++++++++ > gcc/config/loongarch/simd.md | 29 +++++++++++++++++++ > .../gcc.target/loongarch/rotl-with-rotr.c | 9 ++++++ > .../gcc.target/loongarch/rotl-with-vrotr.c | 24 +++++++++++++++ > .../gcc.target/loongarch/rotl-with-xvrotr.c | 7 +++++ > 5 files changed, 81 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c > create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c > create mode 100644 gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c > > diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md > index 30025bf1908..939432b83e0 100644 > --- a/gcc/config/loongarch/loongarch.md > +++ b/gcc/config/loongarch/loongarch.md > @@ -2903,6 +2903,18 @@ (define_insn "rotrsi3_extend" > [(set_attr "type" "shift,shift") > (set_attr "mode" "SI")]) > > +;; Expand left rotate to right rotate. > +(define_expand "rotl3" > + [(set (match_dup 3) > + (neg:SI (match_operand:SI 2 "register_operand"))) > + (set (match_operand:GPR 0 "register_operand") > + (rotatert:GPR (match_operand:GPR 1 "register_operand") > + (match_dup 3)))] > + "" > + { > + operands[3] = gen_reg_rtx (SImode); > + }); > + > ;; The following templates were added to generate "bstrpick.d + alsl.d" > ;; instruction pairs. > ;; It is required that the values of const_immalsl_operand and > diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md > index 13202f79bee..a42e20eb8fc 100644 > --- a/gcc/config/loongarch/simd.md > +++ b/gcc/config/loongarch/simd.md > @@ -268,6 +268,35 @@ (define_insn "vrotr3" > [(set_attr "type" "simd_int_arith") > (set_attr "mode" "")]) > > +;; Expand left rotate to right rotate. > +(define_expand "vrotl3" > + [(set (match_dup 3) > + (neg:IVEC (match_operand:IVEC 2 "register_operand"))) > + (set (match_operand:IVEC 0 "register_operand") > + (rotatert:IVEC (match_operand:IVEC 1 "register_operand") > + (match_dup 3)))] > + "" > + { > + operands[3] = gen_reg_rtx (mode); > + }); > + > +;; Expand left rotate with a scalar amount to right rotate: negate the > +;; scalar before broadcasting it because scalar negation is cheaper than > +;; vector negation. > +(define_expand "rotl3" > + [(set (match_dup 3) > + (neg:SI (match_operand:SI 2 "register_operand"))) > + (set (match_dup 4) > + (vec_duplicate:IVEC (match_dup 3))) > + (set (match_operand:IVEC 0 "register_operand") > + (rotatert:IVEC (match_operand:IVEC 1 "register_operand") > + (match_dup 4)))] > + "" > + { > + operands[3] = gen_reg_rtx (SImode); > + operands[4] = gen_reg_rtx (mode); > + }); > + > ;; vrotri.{b/h/w/d} > > (define_insn "rotr3" > diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c > new file mode 100644 > index 00000000000..84cc53cecaf > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-rotr.c > @@ -0,0 +1,9 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2" } */ > +/* { dg-final { scan-assembler "rotr\\.w" } } */ > + > +unsigned > +t (unsigned a, unsigned b) > +{ > + return a << b | a >> (32 - b); > +} > diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c > new file mode 100644 > index 00000000000..3ebf7e3c083 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-vrotr.c > @@ -0,0 +1,24 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mlsx -fno-vect-cost-model" } */ > +/* { dg-final { scan-assembler-times "vrotr\\.w" 2 } } */ > +/* { dg-final { scan-assembler-times "vneg\\.w" 1 } } */ > + > +#ifndef VLEN > +#define VLEN 16 > +#endif > + > +typedef unsigned int V __attribute__((vector_size(VLEN))); > +V a, b, c; > + > +void > +test (int x) > +{ > + b = a << x | a >> (32 - x); > +} > + > +void > +test2 (void) > +{ > + for (int i = 0; i < VLEN / sizeof (int); i++) > + c[i] = a[i] << b[i] | a[i] >> (32 - b[i]); > +} > diff --git a/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c > new file mode 100644 > index 00000000000..833e041b2e2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/rotl-with-xvrotr.c > @@ -0,0 +1,7 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mlasx -fno-vect-cost-model" } */ > +/* { dg-final { scan-assembler-times "xvrotr\\.w" 2 } } */ > +/* { dg-final { scan-assembler-times "xvneg\\.w" 1 } } */ > + > +#define VLEN 32 > +#include "rotl-with-vrotr.c" --------------EAC82B37AF38AA1EA176071E--