From: Richard Earnshaw <Richard.Earnshaw@foss.arm.com>
To: Ezra.Sitorus@arm.com, gcc-patches@gcc.gnu.org
Cc: richard.earnshaw@arm.com, kyrylo.tkachov@arm.com
Subject: Re: [PATCH 1/3] [GCC] arm: vst1q_types_x2 ACLE intrinsics
Date: Mon, 27 Nov 2023 15:01:13 +0000 [thread overview]
Message-ID: <d94e4b39-aca5-416e-80e2-07b15b61c668@foss.arm.com> (raw)
In-Reply-To: <20231010140445.2084-2-Ezra.Sitorus@arm.com>
On 10/10/2023 15:04, Ezra.Sitorus@arm.com wrote:
> From: Ezra Sitorus <ezra.sitorus@arm.com>
>
> This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for AArch32.
> This patch adds the _x2 variants of the vst1q intrinsic. Tests use xN so that the latter variants (_x3, _x4) could be added.
>
> ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/
> ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/
>
> gcc/ChangeLog:
> * config/arm/arm_neon.h
> (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x32): New.
The same issues that I noted on the previous set apply here too.
Otherwise OK.
R.
> (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
> (vst1q_f16_x2, vst1q_f32_x2): New.
> (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
> (vst1q_bf16_x2): New.
> * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
> * config/arm/neon.md (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from neon_vst1_x2<mode>.
> * config/arm/iterators.md (VMEMX2): New mode iterator.
> (VMEMX2_q): New mode attribute.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests.
> * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests.
> * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests.
> * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests.
> ---
> gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
> gcc/config/arm/arm_neon_builtins.def | 1 +
> gcc/config/arm/iterators.md | 6 +
> gcc/config/arm/neon.md | 6 +-
> .../gcc.target/arm/simd/vst1q_base_xN_1.c | 70 +++++++++++
> .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 13 ++
> .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 13 ++
> .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 13 ++
> 8 files changed, 233 insertions(+), 3 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
> create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
>
> diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
> index 41e645d8352..b8f3fca3060 100644
> --- a/gcc/config/arm/arm_neon.h
> +++ b/gcc/config/arm/arm_neon.h
> @@ -11327,6 +11327,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b)
> __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o);
> }
>
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_s8_x2 (int8_t * __a, int8x16x2_t __b)
> +{
> + union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_s16_x2 (int16_t * __a, int16x8x2_t __b)
> +{
> + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_s32_x2 (int32_t * __a, int32x4x2_t __b)
> +{
> + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b)
> +{
> + union { int64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
> +}
> +
> __extension__ extern __inline void
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
> @@ -11656,6 +11688,14 @@ vst1q_p64 (poly64_t * __a, poly64x2_t __b)
> __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
> }
>
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b)
> +{
> + union { poly64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
> +}
> +
> #pragma GCC pop_options
> __extension__ extern __inline void
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> @@ -11701,6 +11741,24 @@ vst1q_f32 (float32_t * __a, float32x4_t __b)
> __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b);
> }
>
> +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_f16_x2 (float16_t * __a, float16x8x2_t __b)
> +{
> + union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v8hf (__a, __bu.__o);
> +}
> +#endif
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b)
> +{
> + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v4sf (__a, __bu.__o);
> +}
> +
> __extension__ extern __inline void
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vst1q_u8 (uint8_t * __a, uint8x16_t __b)
> @@ -11729,6 +11787,38 @@ vst1q_u64 (uint64_t * __a, uint64x2_t __b)
> __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b);
> }
>
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_u8_x2 (uint8_t * __a, uint8x16x2_t __b)
> +{
> + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_u16_x2 (uint16_t * __a, uint16x8x2_t __b)
> +{
> + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_u32_x2 (uint32_t * __a, uint32x4x2_t __b)
> +{
> + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b)
> +{
> + union { uint64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o);
> +}
> +
> __extension__ extern __inline void
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vst1q_p8 (poly8_t * __a, poly8x16_t __b)
> @@ -11743,6 +11833,22 @@ vst1q_p16 (poly16_t * __a, poly16x8_t __b)
> __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b);
> }
>
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_p8_x2 (poly8_t * __a, poly8x16x2_t __b)
> +{
> + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o);
> +}
> +
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b)
> +{
> + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o);
> +}
> +
> __extension__ extern __inline void
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
> @@ -20419,6 +20525,14 @@ vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b)
> __builtin_neon_vst1v8bf (__a, __b);
> }
>
> +__extension__ extern __inline void
> +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> +vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b)
> +{
> + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b };
> + __builtin_neon_vst1q_x2v8bf (__a, __bu.__o);
> +}
> +
> __extension__ extern __inline void
> __attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
> vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val)
> diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def
> index 95300cb0fe4..496d267fab8 100644
> --- a/gcc/config/arm/arm_neon_builtins.def
> +++ b/gcc/config/arm/arm_neon_builtins.def
> @@ -309,6 +309,7 @@ VAR12 (LOAD1LANE, vld1_lane,
> VAR10 (LOAD1, vld1_dup,
> v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di)
> VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
> +VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
> VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
> VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
> VAR14 (STORE1, vst1,
> diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
> index a9803538101..6c5a80d9348 100644
> --- a/gcc/config/arm/iterators.md
> +++ b/gcc/config/arm/iterators.md
> @@ -141,6 +141,9 @@
> ;; Opaque structure types used in table lookups (except vtbl1/vtbx1).
> (define_mode_iterator VTAB [TI EI OI])
>
> +;; Opaque structure types for x2 variants of VSTR1/VSTR1Q or VLD1/VLD1Q.
> +(define_mode_iterator VMEMX2 [TI OI])
> +
> ;; Widenable modes.
> (define_mode_iterator VW [V8QI V4HI V2SI])
>
> @@ -1533,6 +1536,9 @@
> ;; vtbl<n> suffix for NEON vector modes.
> (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")])
>
> +;; Suffix for x2 variants of vld1 and vst1.
> +(define_mode_attr VMEMX2_q [(TI "") (OI "q")])
> +
> ;; fp16 or bf16 marker for 16-bit float modes.
> (define_mode_attr fporbf [(HF "fp16") (BF "bf16")])
>
> diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
> index f5d583129fa..088277ee6ed 100644
> --- a/gcc/config/arm/neon.md
> +++ b/gcc/config/arm/neon.md
> @@ -5125,9 +5125,9 @@ if (BYTES_BIG_ENDIAN)
> UNSPEC_VST1))]
> "TARGET_NEON")
>
> -(define_insn "neon_vst1_x2<mode>"
> - [(set (match_operand:TI 0 "neon_struct_operand" "=Um")
> - (unspec:TI [(match_operand:TI 1 "s_register_operand" "w")
> +(define_insn "neon_vst1<VMEMX2_q>_x2<VDQX:mode>"
> + [(set (match_operand:VMEMX2 0 "neon_struct_operand" "=Um")
> + (unspec:VMEMX2 [(match_operand:VMEMX2 1 "s_register_operand" "w")
> (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
> UNSPEC_VST1))]
> "TARGET_NEON"
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
> new file mode 100644
> index 00000000000..232feafade0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
> @@ -0,0 +1,70 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target arm_neon_ok } */
> +/* { dg-options "-save-temps -O2" } */
> +/* { dg-add-options arm_neon } */
> +
> +#include "arm_neon.h"
> +
> +
> +void test_vst1q_u8_x2 (uint8_t * ptr, uint8x16x2_t val)
> +{
> + vst1q_u8_x2 (ptr, val);
> +}
> +
> +void test_vst1q_u16_x2 (uint16_t * ptr, uint16x8x2_t val)
> +{
> + vst1q_u16_x2 (ptr, val);
> +}
> +
> +void test_vst1q_u32_x2 (uint32_t * ptr, uint32x4x2_t val)
> +{
> + vst1q_u32_x2 (ptr, val);
> +}
> +
> +void test_vst1q_u64_x2 (uint64_t * ptr, uint64x2x2_t val)
> +{
> + vst1q_u64_x2 (ptr, val);
> +}
> +
> +void test_vst1q_s8_x2 (int8_t * ptr, int8x16x2_t val)
> +{
> + vst1q_s8_x2 (ptr, val);
> +}
> +
> +void test_vst1q_s16_x2 (int16_t * ptr, int16x8x2_t val)
> +{
> + vst1q_s16_x2 (ptr, val);
> +}
> +
> +void test_vst1q_s32_x2 (int32_t * ptr, int32x4x2_t val)
> +{
> + vst1q_s32_x2 (ptr, val);
> +}
> +
> +void test_vst1q_s64_x2 (int64_t * ptr, int64x2x2_t val)
> +{
> + vst1q_s64_x2 (ptr, val);
> +}
> +
> +void test_vst1q_f32_x2 (float32_t * ptr, float32x4x2_t val)
> +{
> + vst1q_f32_x2 (ptr, val);
> +}
> +
> +void test_vst1q_p8_x2 (poly8_t * ptr, poly8x16x2_t val)
> +{
> + vst1q_p8_x2 (ptr, val);
> +}
> +
> +void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val)
> +{
> + vst1q_p16_x2 (ptr, val);
> +}
> +
> +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
> +
> +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
> new file mode 100644
> index 00000000000..2a4579f0aae
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
> @@ -0,0 +1,13 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */
> +/* { dg-options "-save-temps -O2" } */
> +/* { dg-add-options arm_v8_2a_bf16_neon } */
> +
> +#include "arm_neon.h"
> +
> +void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val)
> +{
> + vst1q_bf16_x2 (ptr, val);
> +}
> +
> +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
> new file mode 100644
> index 00000000000..61a7e558c48
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
> @@ -0,0 +1,13 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target arm_neon_fp16_ok } */
> +/* { dg-options "-save-temps -O2" } */
> +/* { dg-add-options arm_neon_fp16 } */
> +
> +#include "arm_neon.h"
> +
> +void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val)
> +{
> + vst1q_f16_x2 (ptr, val);
> +}
> +
> +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
> new file mode 100644
> index 00000000000..82f3dad293c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
> @@ -0,0 +1,13 @@
> +/* { dg-do assemble } */
> +/* { dg-require-effective-target arm_crypto_ok } */
> +/* { dg-options "-save-temps -O2" } */
> +/* { dg-add-options arm_crypto } */
> +
> +#include "arm_neon.h"
> +
> +void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val)
> +{
> + vst1q_p64_x2 (ptr, val);
> +}
> +
> +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */
next prev parent reply other threads:[~2023-11-27 15:01 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 14:04 [PATCH 0/3] [GCC] arm: vst1q_types_xN " Ezra.Sitorus
2023-10-10 14:04 ` [PATCH 1/3] [GCC] arm: vst1q_types_x2 " Ezra.Sitorus
2023-11-27 15:01 ` Richard Earnshaw [this message]
2023-10-10 14:04 ` [PATCH 2/3] [GCC] arm: vst1q_types_x3 " Ezra.Sitorus
2023-11-27 15:02 ` Richard Earnshaw
2023-10-10 14:04 ` [PATCH 3/3] [GCC] arm: vst1q_types_x4 " Ezra.Sitorus
2023-11-27 15:03 ` Richard Earnshaw
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