From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 77503 invoked by alias); 6 Jun 2016 13:41:00 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 77379 invoked by uid 89); 6 Jun 2016 13:40:59 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=BAYES_00,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=vabd_f64, gpf, GPF, backed X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 06 Jun 2016 13:40:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CB99A3B9; Mon, 6 Jun 2016 06:41:21 -0700 (PDT) Received: from [10.2.206.198] (e104437-lin.cambridge.arm.com [10.2.206.198]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C35F33F445; Mon, 6 Jun 2016 06:40:47 -0700 (PDT) From: Jiong Wang Subject: [v2][AArch64, 5/6] Reimplement fabd intrinsics & merge rtl patterns To: James Greenhalgh References: <57430251.6060902@foss.arm.com> <57440F88.2060603@foss.arm.com> <20160527130344.GF26495@arm.com> <57487B41.8020200@foss.arm.com> <6af07de4-8179-c0bf-410c-317ef52876dd@foss.arm.com> <7cb1e234-46f9-76b4-aefd-1eacabfb4ca7@foss.arm.com> <49a7c4d8-3fdc-8806-a4df-affa742cc5d7@foss.arm.com> <32b5ca55-e60a-42b0-3532-84319e5c0daf@foss.arm.com> Cc: GCC Patches Message-ID: Date: Mon, 06 Jun 2016 13:41:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.1.0 MIME-Version: 1.0 In-Reply-To: <32b5ca55-e60a-42b0-3532-84319e5c0daf@foss.arm.com> Content-Type: multipart/mixed; boundary="------------70B65946EC9D3F152AB0403A" X-IsSubscribed: yes X-SW-Source: 2016-06/txt/msg00384.txt.bz2 This is a multi-part message in MIME format. --------------70B65946EC9D3F152AB0403A Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Content-length: 831 These intrinsics were implemented before "fabd_3" introduces. Meanwhile the patterns "fabd_3" and "*fabd_scalar3" can be merged into a single "fabd3" using VALLF. This patch migrate the implementation to builtins backed by this pattern. gcc/ 2016-06-01 Jiong Wang * config/aarch64/aarch64-builtins.def (fabd): New builtins for modes VALLF. * config/aarch64/aarch64-simd.md (fabd_3): Extend modes from VDQF to VALLF. Rename to "fabd3". "*fabd_scalar3): Delete. * config/aarch64/arm_neon.h (vabds_f32): Remove inline assembly. Use builtin. (vabdd_f64): Likewise. (vabd_f32): Likewise. (vabd_f64): Likewise. (vabdq_f32): Likewise. (vabdq_f64): Likewise. --------------70B65946EC9D3F152AB0403A Content-Type: text/x-patch; name="5.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="5.patch" Content-length: 5671 diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 1955d171d727e8995795d343ea766f130be0985e..deab3450ab74fcd6dfcf8267fa9cedfc1423ca4e 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -465,3 +465,6 @@ /* Implemented by aarch64_rsqrts. */ BUILTIN_VALLF (BINOP, rsqrts, 0) + + /* Implemented by fabd3. */ + BUILTIN_VALLF (BINOP, fabd, 3) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 78a87b1fb52b5b5e21ef5cd7dbe090c863369775..ad8b9c1d0c155d022be2e7e7c426120b551f3f2b 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -474,23 +474,14 @@ [(set_attr "type" "neon_arith_acc")] ) -(define_insn "fabd_3" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (abs:VDQF (minus:VDQF - (match_operand:VDQF 1 "register_operand" "w") - (match_operand:VDQF 2 "register_operand" "w"))))] - "TARGET_SIMD" - "fabd\t%0., %1., %2." - [(set_attr "type" "neon_fp_abd_")] -) - -(define_insn "*fabd_scalar3" - [(set (match_operand:GPF 0 "register_operand" "=w") - (abs:GPF (minus:GPF - (match_operand:GPF 1 "register_operand" "w") - (match_operand:GPF 2 "register_operand" "w"))))] +(define_insn "fabd3" + [(set (match_operand:VALLF 0 "register_operand" "=w") + (abs:VALLF + (minus:VALLF + (match_operand:VALLF 1 "register_operand" "w") + (match_operand:VALLF 2 "register_operand" "w"))))] "TARGET_SIMD" - "fabd\t%0, %1, %2" + "fabd\t%0, %1, %2" [(set_attr "type" "neon_fp_abd_")] ) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 2177703180ca50acedd64d613e4e665264371fb2..9e966e47789646ed968a081c1fc4cb76b45537af 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -5440,17 +5440,6 @@ vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c) return result; } -__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) -vabd_f32 (float32x2_t a, float32x2_t b) -{ - float32x2_t result; - __asm__ ("fabd %0.2s, %1.2s, %2.2s" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - __extension__ static __inline int8x8_t __attribute__ ((__always_inline__)) vabd_s8 (int8x8_t a, int8x8_t b) { @@ -5517,17 +5506,6 @@ vabd_u32 (uint32x2_t a, uint32x2_t b) return result; } -__extension__ static __inline float64_t __attribute__ ((__always_inline__)) -vabdd_f64 (float64_t a, float64_t b) -{ - float64_t result; - __asm__ ("fabd %d0, %d1, %d2" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - __extension__ static __inline int16x8_t __attribute__ ((__always_inline__)) vabdl_high_s8 (int8x16_t a, int8x16_t b) { @@ -5660,28 +5638,6 @@ vabdl_u32 (uint32x2_t a, uint32x2_t b) return result; } -__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) -vabdq_f32 (float32x4_t a, float32x4_t b) -{ - float32x4_t result; - __asm__ ("fabd %0.4s, %1.4s, %2.4s" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - -__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) -vabdq_f64 (float64x2_t a, float64x2_t b) -{ - float64x2_t result; - __asm__ ("fabd %0.2d, %1.2d, %2.2d" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - __extension__ static __inline int8x16_t __attribute__ ((__always_inline__)) vabdq_s8 (int8x16_t a, int8x16_t b) { @@ -5748,17 +5704,6 @@ vabdq_u32 (uint32x4_t a, uint32x4_t b) return result; } -__extension__ static __inline float32_t __attribute__ ((__always_inline__)) -vabds_f32 (float32_t a, float32_t b) -{ - float32_t result; - __asm__ ("fabd %s0, %s1, %s2" - : "=w"(result) - : "w"(a), "w"(b) - : /* No clobbers */); - return result; -} - __extension__ static __inline int16_t __attribute__ ((__always_inline__)) vaddlv_s8 (int8x8_t a) { @@ -10235,6 +10180,45 @@ vtbx2_p8 (poly8x8_t r, poly8x8x2_t tab, uint8x8_t idx) /* Start of optimal implementations in approved order. */ +/* vabd. */ + +__extension__ static __inline float32_t __attribute__ ((__always_inline__)) +vabds_f32 (float32_t __a, float32_t __b) +{ + return __builtin_aarch64_fabdsf (__a, __b); +} + +__extension__ static __inline float64_t __attribute__ ((__always_inline__)) +vabdd_f64 (float64_t __a, float64_t __b) +{ + return __builtin_aarch64_fabddf (__a, __b); +} + +__extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) +vabd_f32 (float32x2_t __a, float32x2_t __b) +{ + return __builtin_aarch64_fabdv2sf (__a, __b); +} + +__extension__ static __inline float64x1_t __attribute__ ((__always_inline__)) +vabd_f64 (float64x1_t __a, float64x1_t __b) +{ + return (float64x1_t) {vabdd_f64 (vget_lane_f64 (__a, 0), + vget_lane_f64 (__b, 0))}; +} + +__extension__ static __inline float32x4_t __attribute__ ((__always_inline__)) +vabdq_f32 (float32x4_t __a, float32x4_t __b) +{ + return __builtin_aarch64_fabdv4sf (__a, __b); +} + +__extension__ static __inline float64x2_t __attribute__ ((__always_inline__)) +vabdq_f64 (float64x2_t __a, float64x2_t __b) +{ + return __builtin_aarch64_fabdv2df (__a, __b); +} + /* vabs */ __extension__ static __inline float32x2_t __attribute__ ((__always_inline__)) --------------70B65946EC9D3F152AB0403A--