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Violators will be prosecuted; Mon, 5 Feb 2018 19:07:42 -0500 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w1607gsX49283094; Tue, 6 Feb 2018 00:07:42 GMT Received: from b01ledav004.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 603EC112034; Mon, 5 Feb 2018 19:05:45 -0500 (EST) Received: from otta.local (unknown [9.85.175.62]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP id F27CE112040; Mon, 5 Feb 2018 19:05:44 -0500 (EST) To: GCC Patches Cc: Segher Boessenkool , Bill Schmidt , will_schmidt@vnet.ibm.com From: Peter Bergner Subject: [PATCH, rs6000] Fix PR83926, ICE using __builtin_vsx_{div,udiv,mul}_2di builtins Date: Tue, 06 Feb 2018 00:07:00 -0000 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.13; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 x-cbid: 18020600-2213-0000-0000-0000026819CD X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008479; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000248; SDB=6.00985503; UDB=6.00500052; IPR=6.00764872; BA=6.00005812; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019387; XFM=3.00000015; UTC=2018-02-06 00:07:43 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18020600-2214-0000-0000-000059036EB3 Message-Id: X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-02-05_06:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802060000 X-IsSubscribed: yes X-SW-Source: 2018-02/txt/msg00200.txt.bz2 PR83926 shows a problem in expanding the _builtin_vsx_{div,udiv,mul}_2di builtins in 32-bit mode. The problem is that the splitters for the patterns explicitly call gen_{div,udiv,mul}di3 patterns, even in 32-bit mode and those patterns assume the associated 64-bit HW instructions exist when they do not. The "fix" implemented here is to modify gen_{div,udiv,mul} to catch the case when we have DImode operands in 32-bit mode (and not using -mpowerpc64) and do the right thing. In the case of gen_{div,udiv}di3, that means calling their lib functions and for gen_muldi3, we call expand_mult() which emits code that does the 64-bit multiply. This passes bootstrap and regtesting on powerpc64le-linux, as well as on powerpc64-linux (running the testsuite in both 32-bit and 64-bit modes). Ok for trunk? Peter gcc/ PR target/83926 * config/rs6000/rs6000.md (*mul3): Rename to this... (mul3): ...from this. Declare new define_expand. (*udiv3): Rename to this... (udiv3): ...from this. Declare new define_expand. (div3): Handle DImode operands in 32-bit mode. gcc/testsuite/ PR target/83926 * gcc.target/powerpc/pr83926.c: New test. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 257390) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -2872,8 +2872,21 @@ DONE; }") +(define_expand "mul3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:GPR 2 "reg_or_short_operand" "")))] + "" +{ + if (mode == DImode && !TARGET_POWERPC64) + { + rtx ret = expand_mult (DImode, operands[1], operands[2], NULL, 0, false); + emit_move_insn (operands[0], ret); + DONE; + } +}) -(define_insn "mul3" +(define_insn "*mul3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") (match_operand:GPR 2 "reg_or_short_operand" "r,I")))] @@ -3040,7 +3053,25 @@ "maddld %0,%1,%2,%3" [(set_attr "type" "mul")]) -(define_insn "udiv3" +(define_expand "udiv3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "") + (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") + (match_operand:GPR 2 "gpc_reg_operand" "")))] + "" +{ + if (mode == DImode && !TARGET_POWERPC64) + { + rtx libfunc = optab_libfunc (udiv_optab, mode); + rtx target = emit_library_call_value (libfunc, + operands[0], LCT_NORMAL, mode, + operands[1], mode, + operands[2], mode); + emit_move_insn (operands[0], target); + DONE; + } +}) + +(define_insn "*udiv3" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") (match_operand:GPR 2 "gpc_reg_operand" "r")))] @@ -3066,7 +3097,16 @@ emit_insn (gen_div3_sra (operands[0], operands[1], operands[2])); DONE; } - + else if (mode == DImode && !TARGET_POWERPC64) + { + rtx libfunc = optab_libfunc (sdiv_optab, mode); + rtx target = emit_library_call_value (libfunc, + operands[0], LCT_NORMAL, mode, + operands[1], mode, + operands[2], mode); + emit_move_insn (operands[0], target); + DONE; + } operands[2] = force_reg (mode, operands[2]); }) Index: gcc/testsuite/gcc.target/powerpc/pr83926.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr83926.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr83926.c (working copy) @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-O2 -mcpu=power8 -mno-fold-gimple" } */ + +__attribute__ ((altivec(vector__))) long long +sdiv (__attribute__ ((altivec(vector__))) long long a, + __attribute__ ((altivec(vector__))) long long b) +{ + return __builtin_vsx_div_2di (a, b); +} +__attribute__ ((altivec(vector__))) unsigned long long +udiv (__attribute__ ((altivec(vector__))) unsigned long long a, + __attribute__ ((altivec(vector__))) unsigned long long b) +{ + return __builtin_vsx_udiv_2di (a, b); +} +__attribute__ ((altivec(vector__))) long long +smul (__attribute__ ((altivec(vector__))) long long a, + __attribute__ ((altivec(vector__))) long long b) +{ + return __builtin_vsx_mul_2di (a, b); +}