From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm1-x32d.google.com (mail-wm1-x32d.google.com [IPv6:2a00:1450:4864:20::32d]) by sourceware.org (Postfix) with ESMTPS id 0F92F3860C08 for ; Thu, 26 May 2022 11:58:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0F92F3860C08 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wm1-x32d.google.com with SMTP id n124-20020a1c2782000000b003972dfca96cso945791wmn.4 for ; Thu, 26 May 2022 04:58:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=message-id:date:mime-version:user-agent:to:cc:references:from :subject:in-reply-to:content-transfer-encoding; bh=0flIwyiTDBPVIC7I6PNTjs99ki6a9I5FpLUrkQLVhKM=; b=cNGNJ8rwApEVXA3diq231VL+5Qp3omGmegKV9iC2atM1wcC/T5GArDdtBBX/jRihIP S5mDb1IcyZ6uVW55MRU9kGSp9A/0ijZsdMTHH0ycekG0i/DpcM4KNrkNV3g5JX2blEuo OREeUmAO+0dQxnMudJRSd3e0KmY8d4pTP5w02HBkNDJ0Kgjk9si2sSB3PlTOeMBoXRJ1 7h8dIoM5GZPoMa24eH8V9Urv94+w6ea5qe04yy9kTar4kAnwcIDcvJWc0Va0QSxYPvh+ R+BfYhgn00TW496Ieq/zkoqtGE5Lx58aYqC2sjAqQEJI9C7X/foqQtueZcNo/MuyD3BL ldRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:to:cc :references:from:subject:in-reply-to:content-transfer-encoding; bh=0flIwyiTDBPVIC7I6PNTjs99ki6a9I5FpLUrkQLVhKM=; b=Ko6jyIDiXaQEEXOiG4CbfEFYL9KgiVWsWXAxiuySyM5W3TLHyTXnu/2MLNcL9eY/9w P9Jx+izLyKcnhpc5Xw3K04aCYsLXy9jAQCECoUwWfpYmbeJeEkwOm3uR3ZCBzl86IIpe Om7wyLBXiZGIsfjghgyVXeLrdT3mLciuTxvy6WPFdOaYcb9GY9yVv2DPZ1ppYGpc9q8c Ga+g4s1uIis8jjI8dYRUnVcXc2mL2LtDnIZgXhxQL2xhIjscXPgnUlH7LprbiCmYNIAR S9vbHp1QbAzLOnMRfqGfbZoUZijRJBrIuWWhtTyL87guLZOr0b1QsVSA3Qej/K7aKNUp aw/A== X-Gm-Message-State: AOAM533YPUg0xbPNPpRKOyL1+0U9uE968v4EzqPfcKQlhPbw5VMTuu8i nVhZlw1wtF5M0JygkBoWLpkxEw== X-Google-Smtp-Source: ABdhPJxZ+QzFsTGMLK+GSsq6ID2wQQ54eHhdbGo7CBpzAreuyR0rO458G4fN6J1meTnz2EnRqBATWA== X-Received: by 2002:a1c:f314:0:b0:397:10a5:a355 with SMTP id q20-20020a1cf314000000b0039710a5a355mr1997673wmq.176.1653566297432; Thu, 26 May 2022 04:58:17 -0700 (PDT) Received: from [192.168.0.121] ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id y3-20020a05600015c300b0020e5d8dbbb8sm1710533wry.56.2022.05.26.04.58.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 May 2022 04:58:16 -0700 (PDT) Message-ID: Date: Thu, 26 May 2022 12:58:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 To: shiyulong@iscas.ac.cn, gcc-patches@gcc.gnu.org Cc: andrew@sifive.com, kito.cheng@gmail.com, jiawei@iscas.ac.cn, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn References: <20220510032526.11560-1-shiyulong@iscas.ac.cn> <20220510032526.11560-3-shiyulong@iscas.ac.cn> From: Simon Cook Subject: Re: [PATCH V4 2/3] RISC-V:Cache Management Operation instructions In-Reply-To: <20220510032526.11560-3-shiyulong@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 May 2022 11:58:21 -0000 Hi, I've just tried using these builtins now these have landed in trunk, and I have a question about the cbo builtins. Looking at the code being generated it looks like these builtins return an int and take no arguments, but reading the instructions these should instead take an int and return nothing. As an example using one of the tests, int foo1() { return __builtin_riscv_zicbom_cbo_clean(); } generates foo1: addi sp,sp,-16 sw s0,12(sp) addi s0,sp,16 cbo.clean 0(a5) mv a0,a5 lw s0,12(sp) addi sp,sp,16 jr ra .size foo1, .-foo1 This reads to me like GCC is expecting the cbo.clean to have placed a value in a5, which is then moved to a0 for returning. Is this a bug with these builtins, or have I misunderstood these instructions? Thanks, Simon On 10/05/2022 04:25, shiyulong@iscas.ac.cn wrote: > From: yulong > > This commit adds cbo.clea,cbo.flush,cbo.inval,cbo.zero,prefetch.i,prefetch.r and prefetch.w instructions. > diff with the previous version: > We use unspec_volatile instead of unspec for those cache operations. We use UNSPECV instead of UNSPEC and move them to unspecv. > > gcc/ChangeLog: > > * config/riscv/predicates.md (imm5_operand): Add a new operand type for prefetch instructions. > * config/riscv/riscv-builtins.cc (AVAIL): Add new AVAILs for CMO ISA Extensions. > (RISCV_ATYPE_SI): New. > (RISCV_ATYPE_DI): New. > * config/riscv/riscv-ftypes.def (0): New. > (1): New. > * config/riscv/riscv.md (riscv_clean_): New. > (riscv_flush_): New. > (riscv_inval_): New. > (riscv_zero_): New. > (prefetch): New. > (riscv_prefetchi_): New. > * config/riscv/riscv-cmo.def: New file. > --- > gcc/config/riscv/predicates.md | 4 +++ > gcc/config/riscv/riscv-builtins.cc | 16 ++++++++++ > gcc/config/riscv/riscv-cmo.def | 17 ++++++++++ > gcc/config/riscv/riscv-ftypes.def | 4 +++ > gcc/config/riscv/riscv.md | 51 ++++++++++++++++++++++++++++++ > 5 files changed, 92 insertions(+) > create mode 100644 gcc/config/riscv/riscv-cmo.def > > diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md > index 97cdbdf053b..3fb4d95ab08 100644 > --- a/gcc/config/riscv/predicates.md > +++ b/gcc/config/riscv/predicates.md > @@ -239,3 +239,7 @@ > (define_predicate "const63_operand" > (and (match_code "const_int") > (match_test "INTVAL (op) == 63"))) > + > +(define_predicate "imm5_operand" > + (and (match_code "const_int") > + (match_test "INTVAL (op) < 5"))) > \ No newline at end of file > diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc > index 0658f8d3047..795132a0c16 100644 > --- a/gcc/config/riscv/riscv-builtins.cc > +++ b/gcc/config/riscv/riscv-builtins.cc > @@ -87,6 +87,18 @@ struct riscv_builtin_description { > > AVAIL (hard_float, TARGET_HARD_FLOAT) > > + > +AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT) > +AVAIL (clean64, TARGET_ZICBOM && TARGET_64BIT) > +AVAIL (flush32, TARGET_ZICBOM && !TARGET_64BIT) > +AVAIL (flush64, TARGET_ZICBOM && TARGET_64BIT) > +AVAIL (inval32, TARGET_ZICBOM && !TARGET_64BIT) > +AVAIL (inval64, TARGET_ZICBOM && TARGET_64BIT) > +AVAIL (zero32, TARGET_ZICBOZ && !TARGET_64BIT) > +AVAIL (zero64, TARGET_ZICBOZ && TARGET_64BIT) > +AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT) > +AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT) > + > /* Construct a riscv_builtin_description from the given arguments. > > INSN is the name of the associated instruction pattern, without the > @@ -119,6 +131,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) > /* Argument types. */ > #define RISCV_ATYPE_VOID void_type_node > #define RISCV_ATYPE_USI unsigned_intSI_type_node > +#define RISCV_ATYPE_SI intSI_type_node > +#define RISCV_ATYPE_DI intDI_type_node > > /* RISCV_FTYPE_ATYPESN takes N RISCV_FTYPES-like type codes and lists > their associated RISCV_ATYPEs. */ > @@ -128,6 +142,8 @@ AVAIL (hard_float, TARGET_HARD_FLOAT) > RISCV_ATYPE_##A, RISCV_ATYPE_##B > > static const struct riscv_builtin_description riscv_builtins[] = { > + #include "riscv-cmo.def" > + > DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float), > DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float) > }; > diff --git a/gcc/config/riscv/riscv-cmo.def b/gcc/config/riscv/riscv-cmo.def > new file mode 100644 > index 00000000000..01cbf6ad64f > --- /dev/null > +++ b/gcc/config/riscv/riscv-cmo.def > @@ -0,0 +1,17 @@ > +// zicbom > +RISCV_BUILTIN (clean_si, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, clean32), > +RISCV_BUILTIN (clean_di, "zicbom_cbo_clean", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, clean64), > + > +RISCV_BUILTIN (flush_si, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, flush32), > +RISCV_BUILTIN (flush_di, "zicbom_cbo_flush", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, flush64), > + > +RISCV_BUILTIN (inval_si, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, inval32), > +RISCV_BUILTIN (inval_di, "zicbom_cbo_inval", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, inval64), > + > +// zicboz > +RISCV_BUILTIN (zero_si, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE, zero32), > +RISCV_BUILTIN (zero_di, "zicboz_cbo_zero", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE, zero64), > + > +// zicbop > +RISCV_BUILTIN (prefetchi_si, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, prefetchi32), > +RISCV_BUILTIN (prefetchi_di, "zicbop_cbo_prefetchi", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, prefetchi64), > \ No newline at end of file > diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def > index 2214c496f9b..62421292ce7 100644 > --- a/gcc/config/riscv/riscv-ftypes.def > +++ b/gcc/config/riscv/riscv-ftypes.def > @@ -28,3 +28,7 @@ along with GCC; see the file COPYING3. If not see > > DEF_RISCV_FTYPE (0, (USI)) > DEF_RISCV_FTYPE (1, (VOID, USI)) > +DEF_RISCV_FTYPE (0, (SI)) > +DEF_RISCV_FTYPE (0, (DI)) > +DEF_RISCV_FTYPE (1, (SI, SI)) > +DEF_RISCV_FTYPE (1, (DI, DI)) > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index b3c5bce842a..b96d0c30e59 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -69,6 +69,11 @@ > ;; Stack Smash Protector > UNSPEC_SSP_SET > UNSPEC_SSP_TEST > + UNSPECV_CLEAN > + UNSPECV_FLUSH > + UNSPECV_INVAL > + UNSPECV_ZERO > + UNSPECV_PREI > ]) > > (define_constants > @@ -2863,6 +2868,52 @@ > "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" > [(set_attr "length" "12")]) > > +(define_insn "riscv_clean_" > +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_CLEAN)] > +"TARGET_ZICBOM" > +"cbo.clean\t%a0" > +) > + > +(define_insn "riscv_flush_" > +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_FLUSH)] > +"TARGET_ZICBOM" > +"cbo.flush\t%a0" > +) > + > +(define_insn "riscv_inval_" > +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_INVAL)] > +"TARGET_ZICBOM" > +"cbo.inval\t%a0" > +) > + > +(define_insn "riscv_zero_" > +[(unspec_volatile:X [(match_operand:X 0 "register_operand" "r")] UNSPECV_ZERO)] > +"TARGET_ZICBOZ" > +"cbo.zero\t%a0" > +) > + > +(define_insn "prefetch" > +[(prefetch (match_operand 0 "address_operand" "p") > + (match_operand 1 "imm5_operand" "i") > + (match_operand 2 "const_int_operand" "n"))] > +"TARGET_ZICBOP" > +{ > + switch (INTVAL (operands[1])) > + { > + case 0: return "prefetch.r\t%a0"; > + case 1: return "prefetch.w\t%a0"; > + default: gcc_unreachable (); > + } > +}) > + > +(define_insn "riscv_prefetchi_" > +[(unspec_volatile:X [(match_operand:X 0 "address_operand" "p") > + (match_operand:X 1 "imm5_operand" "i")] > + UNSPECV_PREI)] > +"TARGET_ZICBOP" > +"prefetch.i\t%a0" > +) > + > (include "bitmanip.md") > (include "sync.md") > (include "peephole.md")