From: Bill Schmidt <wschmidt@linux.ibm.com>
To: gcc-patches@gcc.gnu.org
Cc: segher@kernel.crashing.org, dje.gcc@gmail.com
Subject: [PATCH 5/8] rs6000: Fix LE code gen for vec_cnt[lt]z_lsbb [PR95082]
Date: Fri, 28 Jan 2022 11:50:23 -0600 [thread overview]
Message-ID: <dbff48877a4c294df6d9c953669d135ddac0f02c.1643390744.git.wschmidt@linux.ibm.com> (raw)
In-Reply-To: <cover.1643390744.git.wschmidt@linux.ibm.com>
These built-ins were misimplemented as always having big-endian semantics.
Bootstrapped and tested on powerpc64le-linux-gnu with no regressions.
Is this okay for trunk?
Thanks,
Bill
2022-01-18 Bill Schmidt <wschmidt@linux.ibm.com>
gcc/
PR target/95082
* config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Handle
endianness for vclzlsbb and vctzlsbb.
* config/rs6000/rs6000-builtins.def (VCLZLSBB_V16QI): Change
default pattern and indicate a different pattern will be used for
big endian.
(VCLZLSBB_V4SI): Likewise.
(VCLZLSBB_V8HI): Likewise.
(VCTZLSBB_V16QI): Likewise.
(VCTZLSBB_V4SI): Likewise.
(VCTZLSBB_V8HI): Likewise.
gcc/testsuite/
PR target/95082
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Restrict to -mbig.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: New.
* gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: New.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Restrict to -mbig.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: New.
* gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: New.
---
gcc/config/rs6000/rs6000-builtin.cc | 12 ++++++++++++
gcc/config/rs6000/rs6000-builtins.def | 12 ++++++------
.../gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c | 15 +++++++++++++++
.../gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c | 15 +++++++++++++++
.../gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c | 2 +-
.../gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c | 15 +++++++++++++++
.../gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c | 15 +++++++++++++++
10 files changed, 82 insertions(+), 10 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c
create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c
diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc
index 191a6108a5e..163287f2b67 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -3485,6 +3485,18 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */,
icode = CODE_FOR_vsx_store_v8hi;
else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI)
icode = CODE_FOR_vsx_store_v16qi;
+ else if (fcode == RS6000_BIF_VCLZLSBB_V16QI)
+ icode = CODE_FOR_vclzlsbb_v16qi;
+ else if (fcode == RS6000_BIF_VCLZLSBB_V4SI)
+ icode = CODE_FOR_vclzlsbb_v4si;
+ else if (fcode == RS6000_BIF_VCLZLSBB_V8HI)
+ icode = CODE_FOR_vclzlsbb_v8hi;
+ else if (fcode == RS6000_BIF_VCTZLSBB_V16QI)
+ icode = CODE_FOR_vctzlsbb_v16qi;
+ else if (fcode == RS6000_BIF_VCTZLSBB_V4SI)
+ icode = CODE_FOR_vctzlsbb_v4si;
+ else if (fcode == RS6000_BIF_VCTZLSBB_V8HI)
+ icode = CODE_FOR_vctzlsbb_v8hi;
else
gcc_unreachable ();
}
diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def
index cfe31c2e7de..2bb997a5279 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -2551,13 +2551,13 @@
VBPERMD altivec_vbpermd {}
const signed int __builtin_altivec_vclzlsbb_v16qi (vsc);
- VCLZLSBB_V16QI vclzlsbb_v16qi {}
+ VCLZLSBB_V16QI vctzlsbb_v16qi {endian}
const signed int __builtin_altivec_vclzlsbb_v4si (vsi);
- VCLZLSBB_V4SI vclzlsbb_v4si {}
+ VCLZLSBB_V4SI vctzlsbb_v4si {endian}
const signed int __builtin_altivec_vclzlsbb_v8hi (vss);
- VCLZLSBB_V8HI vclzlsbb_v8hi {}
+ VCLZLSBB_V8HI vctzlsbb_v8hi {endian}
const vsc __builtin_altivec_vctzb (vsc);
VCTZB ctzv16qi2 {}
@@ -2572,13 +2572,13 @@
VCTZW ctzv4si2 {}
const signed int __builtin_altivec_vctzlsbb_v16qi (vsc);
- VCTZLSBB_V16QI vctzlsbb_v16qi {}
+ VCTZLSBB_V16QI vclzlsbb_v16qi {endian}
const signed int __builtin_altivec_vctzlsbb_v4si (vsi);
- VCTZLSBB_V4SI vctzlsbb_v4si {}
+ VCTZLSBB_V4SI vclzlsbb_v4si {endian}
const signed int __builtin_altivec_vctzlsbb_v8hi (vss);
- VCTZLSBB_V8HI vctzlsbb_v8hi {}
+ VCTZLSBB_V8HI vclzlsbb_v8hi {endian}
const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc);
VCMPAEB_P vector_ae_v16qi_p {}
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c
index 0faf233425e..dc92d6fdd65 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c
index 201ed17e2fd..6fefb893936 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c
new file mode 100644
index 00000000000..6ee31a11aee
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_leading_zero_byte_bits (vector signed char *arg1_p)
+{
+ vector signed char arg_1 = *arg1_p;
+
+ return vec_cntlz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vctzlsbb" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c
new file mode 100644
index 00000000000..6105091b016
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_leading_zero_byte_bits (vector unsigned char *arg1_p)
+{
+ vector unsigned char arg_1 = *arg1_p;
+
+ return vec_cntlz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vctzlsbb" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c
index 70a398ac401..68d6c5ff4e8 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c
index f6d41e3e728..f971ea0a807 100644
--- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile { target { powerpc*-*-* } } } */
/* { dg-require-effective-target powerpc_p9vector_ok } */
-/* { dg-options "-mdejagnu-cpu=power9" } */
+/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */
#include <altivec.h>
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c
new file mode 100644
index 00000000000..a9245d8200c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_trailing_zero_byte_bits (vector signed char *arg1_p)
+{
+ vector signed char arg_1 = *arg1_p;
+
+ return vec_cnttz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vclzlsbb" } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c
new file mode 100644
index 00000000000..71fea5306c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */
+
+#include <altivec.h>
+
+int
+count_trailing_zero_byte_bits (vector unsigned char *arg1_p)
+{
+ vector unsigned char arg_1 = *arg1_p;
+
+ return vec_cnttz_lsbb (arg_1);
+}
+
+/* { dg-final { scan-assembler "vclzlsbb" } } */
--
2.27.0
next prev parent reply other threads:[~2022-01-28 17:51 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-28 17:50 [PATCH 0/8] rs6000: Built-in function cleanups and bug fixes Bill Schmidt
2022-01-28 17:50 ` [PATCH 1/8] rs6000: More factoring of overload processing Bill Schmidt
2022-01-28 19:11 ` Segher Boessenkool
2022-01-28 21:19 ` Bill Schmidt
2022-01-28 23:09 ` Segher Boessenkool
2022-02-01 14:49 ` [PATCH v2 " Bill Schmidt
2022-02-01 21:48 ` Segher Boessenkool
2022-02-02 18:46 ` Bill Schmidt
2022-02-03 14:44 ` [PATCH v3 " Bill Schmidt
2022-02-04 1:24 ` Segher Boessenkool
2022-01-28 17:50 ` [PATCH 2/8] rs6000: Don't #ifdef "short" built-in names Bill Schmidt
2022-01-28 20:32 ` Segher Boessenkool
2022-01-28 21:21 ` Bill Schmidt
2022-01-28 17:50 ` [PATCH 3/8] rs6000: Convert <x> built-in constraints to <x,y> form Bill Schmidt
2022-01-28 23:24 ` [PATCH 3/8] rs6000: Convert <x> built-in constraints to <x, y> form Segher Boessenkool
2022-01-31 17:21 ` [PATCH 3/8] rs6000: Convert <x> built-in constraints to <x,y> form Bill Schmidt
2022-01-31 17:28 ` [PATCH 3/8] rs6000: Convert <x> built-in constraints to <x, y> form Segher Boessenkool
2022-01-31 17:31 ` [PATCH 3/8] rs6000: Convert <x> built-in constraints to <x,y> form Bill Schmidt
2022-02-01 14:53 ` [PATCH v2 3/8] rs6000: Unify error messages for built-in constant restrictions Bill Schmidt
2022-02-01 22:16 ` Segher Boessenkool
2022-01-28 17:50 ` [PATCH 4/8] rs6000: Consolidate target built-ins code Bill Schmidt
2022-01-31 21:32 ` Segher Boessenkool
2022-01-31 22:01 ` Bill Schmidt
2022-01-31 22:33 ` Segher Boessenkool
2022-01-28 17:50 ` Bill Schmidt [this message]
2022-02-01 23:01 ` [PATCH 5/8] rs6000: Fix LE code gen for vec_cnt[lt]z_lsbb [PR95082] Segher Boessenkool
2022-01-28 17:50 ` [PATCH 6/8] rs6000: Remove -m[no-]fold-gimple flag [PR103686] Bill Schmidt
2022-02-02 23:21 ` Segher Boessenkool
2022-01-28 17:50 ` [PATCH 7/8] rs6000: vec_neg built-ins wrongly require POWER8 Bill Schmidt
2022-02-07 15:48 ` Bill Schmidt
2022-03-30 18:04 ` Segher Boessenkool
2022-01-28 17:50 ` [PATCH 8/8] rs6000: Fix some missing built-in attributes [PR104004] Bill Schmidt
2022-03-15 13:18 ` rs6000 patch ping: " Jakub Jelinek
2022-03-30 12:28 ` rs6000 patch ping^2: " Jakub Jelinek
2022-03-30 23:07 ` rs6000 patch ping: " Segher Boessenkool
2022-03-31 22:17 ` Segher Boessenkool
2022-03-30 17:41 ` will schmidt
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