From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 52E4C3858C31 for ; Mon, 22 May 2023 06:36:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52E4C3858C31 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com Received: from pps.filterd (m0353724.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34M5qGW8007128; Mon, 22 May 2023 06:36:47 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=pp1; bh=qNOx8GTVEPtVK+o+UcSnbex76uHwH1FbD3TNnsxXsiM=; b=iSwINMay1+GgWUv6kN2lqXo8e2/LpzVPdbc349fSGQPArvUZcpac0b206JSjpVrGGIR6 ME1Yi4RMgbriV+BpO/f8BMd0kKNtTCu+5LXUfchu6yqVtcgpDiX5iQw+ZLBSX5yLrBD+ 6QP/K6/PMf86/fidzX5uy992tWf2Rv3aoYjXIFLuYeD+DH/wmBXH/u4V6RnLEJCGa3L1 WOP0CuyHcfOGj1cGGIbgHyBKLNxEv494QjyBGtn8OMFt7S6stqarog6rciYC83g5ffkT DBSF8M5FgIKewHbIOxZwm7DLQf8qMLs6SJXHZkb7Q2+Gj1R6DkMs7k5ZJJtPYTlQKvfR lg== Received: from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com [149.81.74.108]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3qqee6ma7c-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 May 2023 06:36:39 +0000 Received: from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1]) by ppma05fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 34M2vlUk017967; Mon, 22 May 2023 06:36:38 GMT Received: from smtprelay04.fra02v.mail.ibm.com ([9.218.2.228]) by ppma05fra.de.ibm.com (PPS) with ESMTPS id 3qppbmgp60-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 22 May 2023 06:36:37 +0000 Received: from smtpav06.fra02v.mail.ibm.com (smtpav06.fra02v.mail.ibm.com [10.20.54.105]) by smtprelay04.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 34M6aZPO16581356 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 22 May 2023 06:36:35 GMT Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2FA0020049; Mon, 22 May 2023 06:36:35 +0000 (GMT) Received: from smtpav06.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3B5FB20040; Mon, 22 May 2023 06:36:33 +0000 (GMT) Received: from [9.177.82.45] (unknown [9.177.82.45]) by smtpav06.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 22 May 2023 06:36:32 +0000 (GMT) Message-ID: Date: Mon, 22 May 2023 14:36:31 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH v2] rs6000: Add buildin for mffscrn instructions Content-Language: en-US To: Carl Love Cc: Peter Bergner , Segher Boessenkool , gcc-patches@gcc.gnu.org References: From: "Kewen.Lin" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fjEZeHM6JUlY70z0CxmdWe_ULaiFQhDo X-Proofpoint-ORIG-GUID: fjEZeHM6JUlY70z0CxmdWe_ULaiFQhDo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-22_03,2023-05-17_02,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 impostorscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305220051 X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,NICE_REPLY_A,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Carl, on 2023/5/19 05:12, Carl Love via Gcc-patches wrote: > GCC maintainers: > > version 2. Fixed an issue with the test case. The dg-options line was > missing. > > The following patch adds an overloaded builtin. There are two possible > arguments for the builtin. The builtin definitions are: > > double __builtin_mffscrn (unsigned long int); > double __builtin_mffscrn (double); > We already have one bif __builtin_set_fpscr_rn for RN setting, apparently these two are mainly for direct mapping to mffscr[ni] and want the FPSCR bits. I'm curious what's the requirements requesting these two built-in functions? > The patch has been tested on Power 10 with no regressions. > > Please let me know if the patch is acceptable for mainline. Thanks. > > Carl > > ------------------------------------------------ > rs6000: Add buildin for mffscrn instructions > s/buildin/built-in/ > This patch adds overloaded __builtin_mffscrn for the move From FPSCR > Control & Set R instruction with an immediate argument. It also adds the > builtin with a floating point register argument. A new runnable test is > added for the new builtin. s/Set R/Set RN/ > > gcc/ > > * config/rs6000/rs6000-builtins.def (__builtin_mffscrni, > __builtin_mffscrnd): Add builtin definitions. > * config/rs6000/rs6000-overload.def (__builtin_mffscrn): Add > overloaded definition. > * doc/extend.texi: Add documentation for __builtin_mffscrn. > > gcc/testsuite/ > > * gcc.target/powerpc/builtin-mffscrn.c: Add testcase for new > builtin. > --- > gcc/config/rs6000/rs6000-builtins.def | 7 ++ > gcc/config/rs6000/rs6000-overload.def | 5 + > gcc/doc/extend.texi | 8 ++ > .../gcc.target/powerpc/builtin-mffscrn.c | 106 ++++++++++++++++++ > 4 files changed, 126 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c > > diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def > index 92d9b46e1b9..67125473684 100644 > --- a/gcc/config/rs6000/rs6000-builtins.def > +++ b/gcc/config/rs6000/rs6000-builtins.def > @@ -2875,6 +2875,13 @@ > pure vsc __builtin_vsx_xl_len_r (void *, signed long); > XL_LEN_R xl_len_r {} > > +; Immediate instruction only uses the least significant two bits of the > +; const int. > + double __builtin_mffscrni (const int<2>); > + MFFSCRNI rs6000_mffscrni {} > + > + double __builtin_mffscrnd (double); > + MFFSCRNF rs6000_mffscrn {} > Why are them put in [power9-64] rather than [power9]? IMHO [power9] is the correct stanza for them. Besides, {nosoft} attribute is required. > ; Builtins requiring hardware support for IEEE-128 floating-point. > [ieee128-hw] > diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def > index c582490c084..adda2df69ea 100644 > --- a/gcc/config/rs6000/rs6000-overload.def > +++ b/gcc/config/rs6000/rs6000-overload.def > @@ -78,6 +78,11 @@ > ; like after a required newline, but nowhere else. Lines beginning with > ; a semicolon are also treated as blank lines. > > +[MFFSCR, __builtin_mffscrn, __builtin_mffscrn] > + double __builtin_mffscrn (const int<2>); > + MFFSCRNI > + double __builtin_mffscrn (double); > + MFFSCRNF > > [BCDADD, __builtin_bcdadd, __builtin_vec_bcdadd] > vsq __builtin_vec_bcdadd (vsq, vsq, const int); > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index ed8b9c8a87b..f16c046051a 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -18455,6 +18455,9 @@ int __builtin_dfp_dtstsfi_ov_td (unsigned int comparison, _Decimal128 value); > > double __builtin_mffsl(void); > > +double __builtin_mffscrn (unsigned long int); > +double __builtin_mffscrn (double); s/unsigned long int/const int/ Note that this section is for all configurations and your implementation is put __builtin_mffscrn power9 only, so if the intention (requirement) is to make this be for also all configurations, we need to deal with the cases without the support of actual hw insns mffscrn{,i}, just like the existing handlings for mffsl etc. > + > @end smallexample > The @code{__builtin_byte_in_set} function requires a > 64-bit environment supporting ISA 3.0 or later. This function returns > @@ -18511,6 +18514,11 @@ the FPSCR. The instruction is a lower latency version of the @code{mffs} > instruction. If the @code{mffsl} instruction is not available, then the > builtin uses the older @code{mffs} instruction to read the FPSCR. > > +The @code{__builtin_mffscrn} returns the contents of the control bits in the > +FPSCR, bits 29:31 (DRN) and bits 56:63 (VE, OE, UE, ZE, XE, NI, RN). The > +contents of bits [62:63] of the unsigned long int or double argument are placed > +into bits [62:63] of the FPSCR (RN). > + I know this description is copied from ISA doc, but this part is for GCC documentation, the document conventions can be different, I prefer to just describe which control bits in FPSCR like "control bits DRN and VE, OE, UE, ZE, XE, NI, RN in FPSCR are returned with the same locations in FPSCR, RN in FPSCR is set according to the given 2-bits constant for the variant with const int type argument, or the given double whose two bits sits in the same locations of FPSCR RN for the variant with double type argument." > @node Basic PowerPC Built-in Functions Available on ISA 3.1 > @subsubsection Basic PowerPC Built-in Functions Available on ISA 3.1 > > diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c b/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c > new file mode 100644 > index 00000000000..26c666a4091 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/powerpc/builtin-mffscrn.c > @@ -0,0 +1,106 @@ > +/* { dg-do run } */ > +/* { dg-require-effective-target p9vector_hw } */ Since it's nothing about vector, I think you should use p9modulo_hw instead ... > +/* { dg-options "-mpower9-vector -mdejagnu-cpu=power9" } */ ... and it doesn't need -mpower9-vector here. BR, Kewen