* [PATCH] Remove gen_cell_microcode, warn_cell_microcode
@ 2017-05-19 16:59 Segher Boessenkool
0 siblings, 0 replies; only message in thread
From: Segher Boessenkool @ 2017-05-19 16:59 UTC (permalink / raw)
To: gcc-patches; +Cc: dje.gcc, Segher Boessenkool
-mno-gen-cell-microcode is a pain to handle correctly: it causes
different code generation for some very basic patterns, even patterns
specific to that option. It also requires marking up many patterns,
which is a pain when adding new patterns or modifying existing ones
(first non-trivial step is finding the Cell BE manual!)
-mwarn-cell-microcode is very expensive, even more so after my recent
fix for PR43763; and it used to ICE for seven years before that fix.
This patch removes both these command line options (it leaves the
positive form of -mgen-cell-microcode, doing nothing, for
compatibility).
Where cc_reg_not_micro_cr0_operand was used, we now get the regular
cc_reg_not_cr0_operand.
One testcase used -mgen-cell-microcode and one its negation; both
are adjusted.
Tested on powerpc64-linux {-m32,-m64}; is this okay for trunk?
Segher
2017-05-19 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/predicates.md (cc_reg_not_micro_cr0_operand): Delete.
(lwa_operand): Delete rs6000_gen_cell_microcode test.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Delete
rs6000_gen_cell_microcode code.
(rs6000_final_prescan_insn): Delete.
(rs6000_opt_vars): Delete the "gen-cell-microcode" and
"warn-cell-microcode" entries.
* config/rs6000/rs6000.h (FINAL_PRESCAN_INSN): Delete.
* config/rs6000/rs6000.md: Delete rs6000_gen_cell_microcode tests
throughout. Change cc_reg_not_micro_cr0_operand to
cc_reg_not_cr0_operand throughout.
(*extendhi<mode>2_noload): Delete.
* config/rs6000/rs6000.opt (mgen-cell-microcode): Replace by stub.
(mwarn-cell-microcode): Delete.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete
-mgen-cell-microcode and -mwarn-cell-microcode.
gcc/testsuite/
* gcc.target/powerpc/shift-dot.c: Delete -mgen-cell-microcode from
dg-options.
* gfortran.dg/pr80107.f: Delete testcase.
---
gcc/config/rs6000/predicates.md | 21 -----
gcc/config/rs6000/rs6000.c | 51 +-----------
gcc/config/rs6000/rs6000.h | 6 --
gcc/config/rs6000/rs6000.md | 120 +++++++++++----------------
gcc/config/rs6000/rs6000.opt | 8 +-
gcc/doc/invoke.texi | 10 ---
gcc/testsuite/gcc.target/powerpc/shift-dot.c | 2 +-
gcc/testsuite/gfortran.dg/pr80107.f | 6 --
8 files changed, 54 insertions(+), 170 deletions(-)
delete mode 100644 gcc/testsuite/gfortran.dg/pr80107.f
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index e211d3d..961b49f 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -530,25 +530,6 @@ (define_predicate "cc_reg_not_cr0_operand"
return CR_REGNO_NOT_CR0_P (REGNO (op));
})
-;; Return 1 if op is a register that is a condition register field and if generating microcode, not cr0.
-(define_predicate "cc_reg_not_micro_cr0_operand"
- (match_operand 0 "register_operand")
-{
- if (GET_CODE (op) == SUBREG)
- op = SUBREG_REG (op);
-
- if (!REG_P (op))
- return 0;
-
- if (REGNO (op) > LAST_VIRTUAL_REGISTER)
- return 1;
-
- if (rs6000_gen_cell_microcode)
- return CR_REGNO_NOT_CR0_P (REGNO (op));
- else
- return CR_REGNO_P (REGNO (op));
-})
-
;; Return 1 if op is a constant integer valid for D field
;; or non-special register register.
(define_predicate "reg_or_short_operand"
@@ -1069,8 +1050,6 @@ (define_predicate "lwa_operand"
return true;
if (!memory_operand (inner, mode))
return false;
- if (!rs6000_gen_cell_microcode)
- return false;
addr = XEXP (inner, 0);
if (GET_CODE (addr) == PRE_INC
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2161e56..a017afc 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4256,16 +4256,9 @@ rs6000_option_override_internal (bool global_init_p)
error ("SPE not supported in this target");
}
- /* Disable Cell microcode if we are optimizing for the Cell
- and not optimizing for size. */
- if (rs6000_gen_cell_microcode == -1)
- rs6000_gen_cell_microcode = !(rs6000_cpu == PROCESSOR_CELL
- && !optimize_size);
-
- /* If we are optimizing big endian systems for space and it's OK to
- use instructions that would be microcoded on the Cell, use the
- load/store multiple and string instructions. */
- if (BYTES_BIG_ENDIAN && optimize_size && rs6000_gen_cell_microcode)
+ /* If we are optimizing big endian systems for space, use the load/store
+ multiple and string instructions. */
+ if (BYTES_BIG_ENDIAN && optimize_size)
rs6000_isa_flags |= ~rs6000_isa_flags_explicit & (OPTION_MASK_MULTIPLE
| OPTION_MASK_STRING);
@@ -39178,38 +39171,6 @@ rs6000_stack_protect_fail (void)
: default_external_stack_protect_fail ();
}
-void
-rs6000_final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED,
- int num_operands ATTRIBUTE_UNUSED)
-{
- if (rs6000_warn_cell_microcode)
- {
- const char *temp;
- int insn_code_number = recog_memoized (insn);
- location_t location = INSN_LOCATION (insn);
-
- /* Punt on insns we cannot recognize. */
- if (insn_code_number < 0)
- return;
-
- /* get_insn_template can modify recog_data, so save and restore it. */
- struct recog_data_d recog_data_save = recog_data;
- for (int i = 0; i < recog_data.n_operands; i++)
- recog_data.operand[i] = copy_rtx (recog_data.operand[i]);
- temp = get_insn_template (insn_code_number, insn);
- recog_data = recog_data_save;
-
- if (get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS)
- warning_at (location, OPT_mwarn_cell_microcode,
- "emitting microcode insn %s\t[%s] #%d",
- temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
- else if (get_attr_cell_micro (insn) == CELL_MICRO_CONDITIONAL)
- warning_at (location, OPT_mwarn_cell_microcode,
- "emitting conditional microcode insn %s\t[%s] #%d",
- temp, insn_data[INSN_CODE (insn)].name, INSN_UID (insn));
- }
-}
-
/* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
#if TARGET_ELF
@@ -39382,12 +39343,6 @@ static struct rs6000_opt_var const rs6000_opt_vars[] =
{ "sched-epilog",
offsetof (struct gcc_options, x_TARGET_SCHED_PROLOG),
offsetof (struct cl_target_option, x_TARGET_SCHED_PROLOG), },
- { "gen-cell-microcode",
- offsetof (struct gcc_options, x_rs6000_gen_cell_microcode),
- offsetof (struct cl_target_option, x_rs6000_gen_cell_microcode), },
- { "warn-cell-microcode",
- offsetof (struct gcc_options, x_rs6000_warn_cell_microcode),
- offsetof (struct cl_target_option, x_rs6000_warn_cell_microcode), },
};
/* Inner function to handle attribute((target("..."))) and #pragma GCC target
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index ec615e9..d978108 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -2153,12 +2153,6 @@ do { \
/* #define LEGITIMATE_PIC_OPERAND_P (X) */
\f
-/* Define this if some processing needs to be done immediately before
- emitting code for an insn. */
-
-#define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \
- rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS)
-
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
#define CASE_VECTOR_MODE SImode
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3241058..90157a1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -726,7 +726,7 @@ (define_insn_and_split "*zero_extendqi<mode>2_dot"
(compare:CC (zero_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:EXTQI 0 "=r,r"))]
- "rs6000_gen_cell_microcode"
+ ""
"@
andi. %0,%1,0xff
#"
@@ -747,7 +747,7 @@ (define_insn_and_split "*zero_extendqi<mode>2_dot2"
(const_int 0)))
(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
(zero_extend:EXTQI (match_dup 1)))]
- "rs6000_gen_cell_microcode"
+ ""
"@
andi. %0,%1,0xff
#"
@@ -779,7 +779,7 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot"
(compare:CC (zero_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:EXTHI 0 "=r,r"))]
- "rs6000_gen_cell_microcode"
+ ""
"@
andi. %0,%1,0xffff
#"
@@ -800,7 +800,7 @@ (define_insn_and_split "*zero_extendhi<mode>2_dot2"
(const_int 0)))
(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
(zero_extend:EXTHI (match_dup 1)))]
- "rs6000_gen_cell_microcode"
+ ""
"@
andi. %0,%1,0xffff
#"
@@ -835,7 +835,7 @@ (define_insn_and_split "*zero_extendsi<mode>2_dot"
(compare:CC (zero_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:EXTSI 0 "=r,r"))]
- "rs6000_gen_cell_microcode"
+ ""
"@
rldicl. %0,%1,0,32
#"
@@ -856,7 +856,7 @@ (define_insn_and_split "*zero_extendsi<mode>2_dot2"
(const_int 0)))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
(zero_extend:EXTSI (match_dup 1)))]
- "rs6000_gen_cell_microcode"
+ ""
"@
rldicl. %0,%1,0,32
#"
@@ -886,7 +886,7 @@ (define_insn_and_split "*extendqi<mode>2_dot"
(compare:CC (sign_extend:EXTQI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:EXTQI 0 "=r,r"))]
- "rs6000_gen_cell_microcode"
+ ""
"@
extsb. %0,%1
#"
@@ -907,7 +907,7 @@ (define_insn_and_split "*extendqi<mode>2_dot2"
(const_int 0)))
(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r")
(sign_extend:EXTQI (match_dup 1)))]
- "rs6000_gen_cell_microcode"
+ ""
"@
extsb. %0,%1
#"
@@ -932,7 +932,7 @@ (define_expand "extendhi<mode>2"
(define_insn "*extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*wK,?*wK")
(sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,wK")))]
- "rs6000_gen_cell_microcode || TARGET_VSX_SMALL_INTEGER"
+ ""
"@
lha%U1%X1 %0,%1
extsh %0,%1
@@ -955,19 +955,12 @@ (define_split
operands[2] = gen_rtx_REG (HImode, REGNO (operands[1]));
})
-(define_insn "*extendhi<mode>2_noload"
- [(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r")
- (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r")))]
- "!rs6000_gen_cell_microcode"
- "extsh %0,%1"
- [(set_attr "type" "exts")])
-
(define_insn_and_split "*extendhi<mode>2_dot"
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
(compare:CC (sign_extend:EXTHI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:EXTHI 0 "=r,r"))]
- "rs6000_gen_cell_microcode"
+ ""
"@
extsh. %0,%1
#"
@@ -988,7 +981,7 @@ (define_insn_and_split "*extendhi<mode>2_dot2"
(const_int 0)))
(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r")
(sign_extend:EXTHI (match_dup 1)))]
- "rs6000_gen_cell_microcode"
+ ""
"@
extsh. %0,%1
#"
@@ -1052,7 +1045,7 @@ (define_insn_and_split "*extendsi<mode>2_dot"
(compare:CC (sign_extend:EXTSI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:EXTSI 0 "=r,r"))]
- "rs6000_gen_cell_microcode"
+ ""
"@
extsw. %0,%1
#"
@@ -1073,7 +1066,7 @@ (define_insn_and_split "*extendsi<mode>2_dot2"
(const_int 0)))
(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r")
(sign_extend:EXTSI (match_dup 1)))]
- "rs6000_gen_cell_microcode"
+ ""
"@
extsw. %0,%1
#"
@@ -1941,7 +1934,7 @@ (define_insn_and_split "*one_cmpl<mode>2_dot"
(compare:CC (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
not. %0,%1
#"
@@ -1962,7 +1955,7 @@ (define_insn_and_split "*one_cmpl<mode>2_dot2"
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(not:GPR (match_dup 1)))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
not. %0,%1
#"
@@ -2849,7 +2842,7 @@ (define_insn_and_split "*mul<mode>3_dot"
(match_operand:GPR 2 "gpc_reg_operand" "r,r"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
mull<wd>. %0,%1,%2
#"
@@ -2874,7 +2867,7 @@ (define_insn_and_split "*mul<mode>3_dot2"
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(mult:GPR (match_dup 1)
(match_dup 2)))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
mull<wd>. %0,%1,%2
#"
@@ -3220,8 +3213,7 @@ (define_expand "and<mode>3"
DONE;
}
- if (logical_const_operand (operands[2], <MODE>mode)
- && rs6000_gen_cell_microcode)
+ if (logical_const_operand (operands[2], <MODE>mode))
{
emit_insn (gen_and<mode>3_imm (operands[0], operands[1], operands[2]));
DONE;
@@ -3243,8 +3235,7 @@ (define_insn "and<mode>3_imm"
(and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r")
(match_operand:GPR 2 "logical_const_operand" "n")))
(clobber (match_scratch:CC 3 "=x"))]
- "rs6000_gen_cell_microcode
- && !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
+ "!rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
"andi%e2. %0,%1,%u2"
[(set_attr "type" "logical")
(set_attr "dot" "yes")])
@@ -3257,7 +3248,6 @@ (define_insn_and_split "*and<mode>3_imm_dot"
(clobber (match_scratch:GPR 0 "=r,r"))
(clobber (match_scratch:CC 4 "=X,x"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
@@ -3285,7 +3275,6 @@ (define_insn_and_split "*and<mode>3_imm_dot2"
(match_dup 2)))
(clobber (match_scratch:CC 4 "=X,x"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& !rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
@@ -3310,7 +3299,6 @@ (define_insn_and_split "*and<mode>3_imm_mask_dot"
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
@@ -3336,7 +3324,6 @@ (define_insn_and_split "*and<mode>3_imm_mask_dot2"
(and:GPR (match_dup 1)
(match_dup 2)))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
@@ -3366,8 +3353,7 @@ (define_insn "*and<mode>3_imm_dot_shifted"
<< INTVAL (operands[4])),
DImode)
&& (<MODE>mode == Pmode
- || (UINTVAL (operands[2]) << INTVAL (operands[4])) <= 0x7fffffff)
- && rs6000_gen_cell_microcode"
+ || (UINTVAL (operands[2]) << INTVAL (operands[4])) <= 0x7fffffff)"
{
operands[2] = GEN_INT (UINTVAL (operands[2]) << INTVAL (operands[4]));
return "andi%e2. %0,%1,%u2";
@@ -3393,7 +3379,6 @@ (define_insn_and_split "*and<mode>3_mask_dot"
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& !logical_const_operand (operands[2], <MODE>mode)
&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
{
@@ -3423,7 +3408,6 @@ (define_insn_and_split "*and<mode>3_mask_dot2"
(and:GPR (match_dup 1)
(match_dup 2)))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& !logical_const_operand (operands[2], <MODE>mode)
&& rs6000_is_valid_and_mask (operands[2], <MODE>mode)"
{
@@ -3451,8 +3435,7 @@ (define_insn_and_split "*and<mode>3_2insn"
(match_operand:GPR 2 "const_int_operand" "n")))]
"rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
- || (logical_const_operand (operands[2], <MODE>mode)
- && rs6000_gen_cell_microcode))"
+ || logical_const_operand (operands[2], <MODE>mode))"
"#"
"&& 1"
[(pc)]
@@ -3470,11 +3453,9 @@ (define_insn_and_split "*and<mode>3_2insn_dot"
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
- || (logical_const_operand (operands[2], <MODE>mode)
- && rs6000_gen_cell_microcode))"
+ || logical_const_operand (operands[2], <MODE>mode))"
"#"
"&& reload_completed"
[(pc)]
@@ -3495,11 +3476,9 @@ (define_insn_and_split "*and<mode>3_2insn_dot2"
(and:GPR (match_dup 1)
(match_dup 2)))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& rs6000_is_valid_2insn_and (operands[2], <MODE>mode)
&& !(rs6000_is_valid_and_mask (operands[2], <MODE>mode)
- || (logical_const_operand (operands[2], <MODE>mode)
- && rs6000_gen_cell_microcode))"
+ || logical_const_operand (operands[2], <MODE>mode))"
"#"
"&& reload_completed"
[(pc)]
@@ -3592,7 +3571,7 @@ (define_insn_and_split "*bool<mode>3_dot"
(match_operand:GPR 2 "gpc_reg_operand" "r,r")])
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
%q3. %0,%1,%2
#"
@@ -3615,7 +3594,7 @@ (define_insn_and_split "*bool<mode>3_dot2"
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(match_dup 3))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
%q3. %0,%1,%2
#"
@@ -3647,7 +3626,7 @@ (define_insn_and_split "*boolc<mode>3_dot"
(match_operand:GPR 1 "gpc_reg_operand" "r,r")])
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
%q3. %0,%1,%2
#"
@@ -3670,7 +3649,7 @@ (define_insn_and_split "*boolc<mode>3_dot2"
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(match_dup 3))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
%q3. %0,%1,%2
#"
@@ -3702,7 +3681,7 @@ (define_insn_and_split "*boolcc<mode>3_dot"
(not:GPR (match_operand:GPR 2 "gpc_reg_operand" "r,r"))])
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
%q3. %0,%1,%2
#"
@@ -3725,7 +3704,7 @@ (define_insn_and_split "*boolcc<mode>3_dot2"
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(match_dup 3))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
%q3. %0,%1,%2
#"
@@ -3775,7 +3754,6 @@ (define_insn_and_split "*rotl<mode>3_mask_dot"
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
"(<MODE>mode == Pmode || UINTVAL (operands[3]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
{
if (which_alternative == 0)
@@ -3808,7 +3786,6 @@ (define_insn_and_split "*rotl<mode>3_mask_dot2"
(and:GPR (match_dup 4)
(match_dup 3)))]
"(<MODE>mode == Pmode || UINTVAL (operands[3]) <= 0x7fffffff)
- && rs6000_gen_cell_microcode
&& rs6000_is_valid_shift_mask (operands[3], operands[4], <MODE>mode)"
{
if (which_alternative == 0)
@@ -4065,7 +4042,7 @@ (define_insn_and_split "*rotl<mode>3_dot"
(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
rotl<wd>%I2. %0,%1,%<hH>2
#"
@@ -4090,7 +4067,7 @@ (define_insn_and_split "*rotl<mode>3_dot2"
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(rotate:GPR (match_dup 1)
(match_dup 2)))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
rotl<wd>%I2. %0,%1,%<hH>2
#"
@@ -4133,7 +4110,7 @@ (define_insn_and_split "*ashl<mode>3_dot"
(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
sl<wd>%I2. %0,%1,%<hH>2
#"
@@ -4158,7 +4135,7 @@ (define_insn_and_split "*ashl<mode>3_dot2"
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(ashift:GPR (match_dup 1)
(match_dup 2)))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
sl<wd>%I2. %0,%1,%<hH>2
#"
@@ -4322,7 +4299,7 @@ (define_insn_and_split "*lshr<mode>3_dot"
(match_operand:SI 2 "reg_or_cint_operand" "rn,rn"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
sr<wd>%I2. %0,%1,%<hH>2
#"
@@ -4347,7 +4324,7 @@ (define_insn_and_split "*lshr<mode>3_dot2"
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(lshiftrt:GPR (match_dup 1)
(match_dup 2)))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
sr<wd>%I2. %0,%1,%<hH>2
#"
@@ -4393,7 +4370,7 @@ (define_insn_and_split "*ashr<mode>3_dot"
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))
(clobber (reg:GPR CA_REGNO))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
sra<wd>%I2. %0,%1,%<hH>2
#"
@@ -4420,7 +4397,7 @@ (define_insn_and_split "*ashr<mode>3_dot2"
(ashiftrt:GPR (match_dup 1)
(match_dup 2)))
(clobber (reg:GPR CA_REGNO))]
- "<MODE>mode == Pmode && rs6000_gen_cell_microcode"
+ "<MODE>mode == Pmode"
"@
sra<wd>%I2. %0,%1,%<hH>2
#"
@@ -7061,10 +7038,10 @@ (define_insn "*mov<mode>_internal2"
(set_attr "length" "4,4,8")])
(define_split
- [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
- (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
+ [(set (match_operand:CC 2 "cc_reg_not_cr0_operand")
+ (compare:CC (match_operand:P 1 "gpc_reg_operand")
(const_int 0)))
- (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
+ (set (match_operand:P 0 "gpc_reg_operand") (match_dup 1))]
"reload_completed"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2)
@@ -9610,8 +9587,7 @@ (define_insn "*movsi_update2"
(match_operand:DI 2 "gpc_reg_operand" "r")))))
(set (match_operand:DI 0 "gpc_reg_operand" "=b")
(plus:DI (match_dup 1) (match_dup 2)))]
- "TARGET_POWERPC64 && rs6000_gen_cell_microcode
- && !avoiding_indexed_address_p (DImode)"
+ "TARGET_POWERPC64 && !avoiding_indexed_address_p (DImode)"
"lwaux %3,%0,%2"
[(set_attr "type" "load")
(set_attr "sign_extend" "yes")
@@ -9692,9 +9668,9 @@ (define_insn "*movhi_update3"
(match_operand:SI 2 "reg_or_short_operand" "r,I")))))
(set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
(plus:SI (match_dup 1) (match_dup 2)))]
- "TARGET_UPDATE && rs6000_gen_cell_microcode
- && (!avoiding_indexed_address_p (SImode)
- || !gpc_reg_operand (operands[2], SImode))"
+ "TARGET_UPDATE
+ && !(avoiding_indexed_address_p (SImode)
+ && gpc_reg_operand (operands[2], SImode))"
"@
lhaux %3,%0,%2
lhau %3,%2(%0)"
@@ -12341,14 +12317,14 @@ (define_insn ""
(set_attr "length" "8,16")])
(define_split
- [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
+ [(set (match_operand:CC 0 "cc_reg_not_cr0_operand")
(compare:CC
(ashift:SI (match_operator:SI 1 "scc_comparison_operator"
- [(match_operand 2 "cc_reg_operand" "")
+ [(match_operand 2 "cc_reg_operand")
(const_int 0)])
- (match_operand:SI 3 "const_int_operand" ""))
+ (match_operand:SI 3 "const_int_operand"))
(const_int 0)))
- (set (match_operand:SI 4 "gpc_reg_operand" "")
+ (set (match_operand:SI 4 "gpc_reg_operand")
(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
(match_dup 3)))]
"reload_completed"
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index a232d57..fdac5c7 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -441,13 +441,9 @@ mlongcall
Target Report Var(rs6000_default_long_calls) Save
Avoid all range limits on call instructions.
+; This option existed in the past, but now is always on.
mgen-cell-microcode
-Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save
-Generate Cell microcode.
-
-mwarn-cell-microcode
-Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save
-Warn when a Cell microcoded instruction is emitted.
+Target RejectNegative Undocumented Ignore
mwarn-altivec-long
Target Var(rs6000_warn_altivec_long) Init(1) Save
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 715830a..cab295b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1021,7 +1021,6 @@ See RS/6000 and PowerPC Options.
-mspe -mno-spe @gol
-mspe=yes -mspe=no @gol
-mpaired @gol
--mgen-cell-microcode -mwarn-cell-microcode @gol
-mvrsave -mno-vrsave @gol
-mmulhw -mno-mulhw @gol
-mdlmzb -mno-dlmzb @gol
@@ -21270,15 +21269,6 @@ corresponding to the endianness for the target.
@opindex mno-vrsave
Generate VRSAVE instructions when generating AltiVec code.
-@item -mgen-cell-microcode
-@opindex mgen-cell-microcode
-Generate Cell microcode instructions.
-
-@item -mwarn-cell-microcode
-@opindex mwarn-cell-microcode
-Warn when a Cell microcode instruction is emitted. An example
-of a Cell microcode instruction is a variable shift.
-
@item -msecure-plt
@opindex msecure-plt
Generate code that allows @command{ld} and @command{ld.so}
diff --git a/gcc/testsuite/gcc.target/powerpc/shift-dot.c b/gcc/testsuite/gcc.target/powerpc/shift-dot.c
index 002948c..726b7a9 100644
--- a/gcc/testsuite/gcc.target/powerpc/shift-dot.c
+++ b/gcc/testsuite/gcc.target/powerpc/shift-dot.c
@@ -1,7 +1,7 @@
/* Check that record-form instructions are used. */
/* { dg-do compile } */
-/* { dg-options "-O2 -mgen-cell-microcode" } */
+/* { dg-options "-O2" } */
/* { dg-final { scan-assembler-times {\mrotl[wd]\.} 2 } } */
/* { dg-final { scan-assembler-times {\msl[wd]\.} 2 } } */
diff --git a/gcc/testsuite/gfortran.dg/pr80107.f b/gcc/testsuite/gfortran.dg/pr80107.f
deleted file mode 100644
index 541fba8..0000000
--- a/gcc/testsuite/gfortran.dg/pr80107.f
+++ /dev/null
@@ -1,6 +0,0 @@
-! { dg-do compile { target { powerpc*-*-* } } }
-! { dg-options "-O0 -mpower9-dform-vector -mno-gen-cell-microcode" }
-
- integer(kind=2) j, j2, ja
- call c_c(CMPLX(j),(1.,0.),'CMPLX(integer(2))')
- end
--
1.9.3
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2017-05-19 16:59 [PATCH] Remove gen_cell_microcode, warn_cell_microcode Segher Boessenkool
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