From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id C30193858294 for ; Fri, 5 Aug 2022 15:45:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C30193858294 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E8C7106F; Fri, 5 Aug 2022 08:45:50 -0700 (PDT) Received: from [10.2.78.27] (unknown [10.2.78.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C389B3F73B; Fri, 5 Aug 2022 08:45:48 -0700 (PDT) Message-ID: Date: Fri, 5 Aug 2022 16:45:47 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [GCC][PATCH] arm: Add support for Arm Cortex-M85 CPU. Content-Language: en-GB To: Srinath Parvathaneni , gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com References: <94f1da3d-5a66-4919-92c5-563e3a49f455@AZ-NEU-EX04.Arm.com> From: Richard Earnshaw In-Reply-To: <94f1da3d-5a66-4919-92c5-563e3a49f455@AZ-NEU-EX04.Arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3496.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH, KAM_SHORT, NICE_REPLY_A, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 05 Aug 2022 15:45:51 -0000 On 05/08/2022 16:20, Srinath Parvathaneni via Gcc-patches wrote: > Hi, > > This patch adds the -mcpu support for the Arm Cortex-M85 CPU which is an > Armv8.1-M Mainline CPU supporting MVE and PACBTI by default. > > -mpcu=cortex-m85 switch by default matches to -march=armv8.1-m.main+pacbti+mve.fp+fp.dp. > > Also following options are provided to disable default features. > +nomve.fp (disables MVE Floating point) > +nomve (disables MVE Integer and MVE Floating point) > +nodsp (disables dsp, MVE Integer and MVE Floating point) > +nopacbti (disables pacbti) > +nofp (disables floating point and MVE floating point) > > Regression tested on arm-none-eabi and bootstrapped on arm-none-linux-gnueabihf. > > Ok for master? > > Regards, > Srinath. > > gcc/ChangeLog: > > 2022-08-05 Srinath Parvathaneni > > * config/arm/arm-cpus.in (cortex-m85): Define new cpu. CPU is an acronym, so: s/new cpu/new CPU/ > * config/arm/arm-tables.opt: Regenerate. > * config/arm/arm-tune.md: Likewise. > * config/arm/t-rmprofile: Re-use multilibs. > * doc/invoke.texi (Arm Options): Document -mcpu=cortex-m85. > * (-mfix-cmse-cve-2021-35465): Likewise. > > gcc/testsuite/ChangeLog: > > 2022-08-05 Srinath Parvathaneni > > * gcc.target/arm/multilib.exp: Add tests for cortex-m85. > > > ############### Attachment also inlined for ease of reply ############### > > > diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in > index 9502a34fa974744f02ded4f32c03de6169950120..a6f364309f8728d6d2264b4e60feb75d51b87b64 100644 > --- a/gcc/config/arm/arm-cpus.in > +++ b/gcc/config/arm/arm-cpus.in > @@ -1643,6 +1643,21 @@ begin cpu cortex-m55 > vendor 41 > end cpu cortex-m55 > > +begin cpu cortex-m85 > + cname cortexm85 > + tune flags LDSCHED > + architecture armv8.1-m.main+pacbti+mve.fp+fp.dp > + option nopacbti remove pacbti > + option nomve.fp remove mve_float > + option nomve remove mve mve_float > + option nofp remove ALL_FP mve_float > + option nodsp remove MVE mve_float > + isa quirk_no_asmcpu quirk_vlldm > + costs v7m > + part 0xd23 > + vendor 41 > +end cpu cortex-m85 > + > # V8 R-profile implementations. > begin cpu cortex-r52 > cname cortexr52 > diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt > index ef0cc5ef0c87ce37958fc0ac9b1623078b890187..54f87da7852b3e495da9fd08106d9f6bd7c99716 100644 > --- a/gcc/config/arm/arm-tables.opt > +++ b/gcc/config/arm/arm-tables.opt > @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) > EnumValue > Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) > > +EnumValue > +Enum(processor_type) String(cortex-m85) Value( TARGET_CPU_cortexm85) > + > EnumValue > Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) > > diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md > index 3422553604245035089e4f52b3feb9db4c51b2b5..27cafe9b4caf9270cb5f537c988d57715495a207 100644 > --- a/gcc/config/arm/arm-tune.md > +++ b/gcc/config/arm/arm-tune.md > @@ -49,6 +49,6 @@ > cortexa710,cortexx1,neoversen1, > cortexa75cortexa55,cortexa76cortexa55,neoversev1, > neoversen2,cortexm23,cortexm33, > - cortexm35p,cortexm55,cortexr52, > + cortexm35p,cortexm55,cortexm85,cortexr52, > cortexr52plus" > (const (symbol_ref "((enum attr_tune) arm_tune)"))) > diff --git a/gcc/config/arm/t-rmprofile b/gcc/config/arm/t-rmprofile > index fe46a1efa1a8b212e6f4051283573debfc386ff8..77e248e47feeddb2328a82aec6b485ff0f6fd62e 100644 > --- a/gcc/config/arm/t-rmprofile > +++ b/gcc/config/arm/t-rmprofile > @@ -97,6 +97,13 @@ MULTILIB_MATCHES += $(foreach FP, $(v8_1m_sp_variants), \ > MULTILIB_MATCHES += $(foreach FP, $(v8_1m_dp_variants), \ > march?armv8-m.main+fp.dp=mlibarch?armv8.1-m.main$(FP)) > > +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti+fp.dp=march?armv8.1-m.main+pacbti+fp.dp+mve.fp > +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti+fp.dp=mlibarch?armv8.1-m.main+pacbti+fp.dp+mve.fp > +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti+fp.dp=march?armv8.1-m.main+pacbti+fp.dp+mve > +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti+fp.dp=mlibarch?armv8.1-m.main+pacbti+fp.dp+mve > +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti+fp.dp=march?armv8.1-m.main+dsp+pacbti+fp.dp > +MULTILIB_MATCHES += march?armv8.1-m.main+pacbti+fp.dp=mlibarch?armv8.1-m.main+dsp+pacbti+fp.dp > + This seems like generic pac/bti support in armv8.1-m.main, so should be a separate patch from the cortex-m85 support. There should also be tests for these cases when -march= is used rather than -mcpu in multilib.exp > # Map all mbranch-protection values other than 'none' to 'standard'. > MULTILIB_MATCHES += mbranch-protection?standard=mbranch-protection?bti > MULTILIB_MATCHES += mbranch-protection?standard=mbranch-protection?pac-ret > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index a2be3446594822f0b13dc7ba92ada4213a3a965c..47988ca6bedccc8efd1801a784d4f313959e8bb4 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -21079,7 +21079,7 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t}, > @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus}, > @samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3}, > @samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33}, > -@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-x1}, > +@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-m85}, @samp{cortex-x1}, > @samp{cortex-m1.small-multiply}, @samp{cortex-m0.small-multiply}, > @samp{cortex-m0plus.small-multiply}, @samp{exynos-m1}, @samp{marvell-pj4}, > @samp{neoverse-n1}, @samp{neoverse-n2}, @samp{neoverse-v1}, @samp{xscale}, > @@ -21490,8 +21490,9 @@ Development Tools Engineering Specification", which can be found on > Mitigate against a potential security issue with the @code{VLLDM} instruction > in some M-profile devices when using CMSE (CVE-2021-365465). This option is > enabled by default when the option @option{-mcpu=} is used with > -@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55}. The option > -@option{-mno-fix-cmse-cve-2021-35465} can be used to disable the mitigation. > +@code{cortex-m33}, @code{cortex-m35p} or @code{cortex-m55} or @samp{cortex-m85}. > +The option @option{-mno-fix-cmse-cve-2021-35465} can be used to disable the > +mitigation. You're missing the documentation on the various +no... options under -mcpu=. > > @item -mstack-protector-guard=@var{guard} > @itemx -mstack-protector-guard-offset=@var{offset} > diff --git a/gcc/testsuite/gcc.target/arm/multilib.exp b/gcc/testsuite/gcc.target/arm/multilib.exp > index 52e67446453fb420007cf9481cb668e9a3e4f07f..2a682d9704488f5a1817ff8444ba74bced660676 100644 > --- a/gcc/testsuite/gcc.target/arm/multilib.exp > +++ b/gcc/testsuite/gcc.target/arm/multilib.exp > @@ -967,6 +967,31 @@ if {[multilib_config "rmprofile"] } { > {-march=armv8.1-m.main+mve.fp+fp.dp+cdecp0 -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" > {-march=armv8.1-m.main+mve+fp.dp+cdecp0 -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" > {-march=armv8.1-m.main+mve.fp+fp.dp+cdecp0 -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" > + {-mcpu=cortex-m85 -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard" > + {-mcpu=cortex-m85 -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp" > + {-mcpu=cortex-m85+nomve.fp -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard" > + {-mcpu=cortex-m85+nomve.fp -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp" > + {-mcpu=cortex-m85+nomve -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard" > + {-mcpu=cortex-m85+nomve -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp" > + {-mcpu=cortex-m85+nodsp -mbranch-protection=standard -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/hard" > + {-mcpu=cortex-m85+nodsp -mbranch-protection=standard -mfpu=auto -mfloat-abi=softfp} "thumb/v8.1-m.main+pacbti+dp/mbranch-protection/softfp" > + {-mcpu=cortex-m85+nodsp -mbranch-protection=standard -mfpu=auto -mfloat-abi=soft} "thumb/v8.1-m.main+pacbti/mbranch-protection/nofp" > + {-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" > + {-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" > + {-mcpu=cortex-m85+nopacbti -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" > + {-mcpu=cortex-m85+nopacbti+nomve.fp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" > + {-mcpu=cortex-m85+nopacbti+nomve.fp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" > + {-mcpu=cortex-m85+nopacbti+nomve.fp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" > + {-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" > + {-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" > + {-mcpu=cortex-m85+nopacbti+nomve -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" > + {-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=hard} "thumb/v8.1-m.main+mve/hard" > + {-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main/nofp" > + {-mcpu=cortex-m85+nopacbti+nofp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" > + {-mcpu=cortex-m85+nopacbti+nodsp -mfpu=auto -mfloat-abi=hard} "thumb/v8-m.main+dp/hard" > + {-mcpu=cortex-m85+nopacbti+nodsp -mfpu=auto -mfloat-abi=softfp} "thumb/v8-m.main+dp/softfp" > + {-mcpu=cortex-m85+nopacbti+nodsp -mfpu=auto -mfloat-abi=soft} "thumb/v8-m.main/nofp" > + > } { > check_multi_dir $opts $dir > } > > > R.