From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 82A523857034 for ; Thu, 23 Nov 2023 12:08:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 82A523857034 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 82A523857034 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700741295; cv=none; b=A7XWgGpIteusd5yvPC9BwItPKT2F4LfRDGppjFDta7i+TJurDygxHVFNyYlkjqKZpgYOP0ag5brvUbNXp9yMQm+q9gmc4iqArxoapK3iT5trmLS6LqBIUBxjiPdSP3WPh33BFLEsNIRRgHozBoyrsevN6IChjJsS2njYVXuxOGU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1700741295; c=relaxed/simple; bh=KKLiSCLZlSV4fj13h5YJq9H2lqn1B7XhpcOiRyEbV/A=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=k7YZlyGrPCK7nzKJnT4J/TYwBc2Fr7kH0QYoppLerkUiR2ioYWq8ysdRMJKM9mmbDO63SZ81YwyNzlbV0aF9HR1zKFtNpDVDg6HyD1n3ALWoJwxCckUBQKX9MQs/KuVB+EEwOI+q67ODUaBxPuN+giAXhcRfVXORbyGNIUJU+7Q= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8CxRuilQF9l6UY8AA--.280S3; Thu, 23 Nov 2023 20:08:06 +0800 (CST) Received: from [10.20.4.107] (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxE+SgQF9l6bRKAA--.35684S3; Thu, 23 Nov 2023 20:08:01 +0800 (CST) Subject: Re: [PATCH v3 2/5] LoongArch: Use standard pattern name and RTX code for LSX/LASX muh instructions To: Xi Ruoyao , gcc-patches@gcc.gnu.org Cc: i@xen0n.name, xuchenghua@loongson.cn References: <20231120004728.205167-1-xry111@xry111.site> <20231120004728.205167-3-xry111@xry111.site> From: chenglulu Message-ID: Date: Thu, 23 Nov 2023 20:08:00 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20231120004728.205167-3-xry111@xry111.site> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8BxE+SgQF9l6bRKAA--.35684S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3tw4UuFWktr43ZFyDGFy3GFX_yoWkGFyfp3 y7C3WqyFWUJFnFgw18Jay5Xr4rt3s7Jr4UZ3y7uwnrAa1jq3WfuF10ka97XFyaqw1rGryI 93yrXa1YvrWDu3cCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUvIb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AK xVW8Jr0_Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx 1l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv 67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07 AlzVAYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02 F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw 1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7Cj xVAFwI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r 4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x07Ui iSdUUUUU= X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: LGTM. Thanks! ÔÚ 2023/11/20 ÉÏÎç8:47, Xi Ruoyao дµÀ: > Removes unnecessary UNSPECs and make the muh instructions useful with > GNU vectors or auto vectorization. > > gcc/ChangeLog: > > * config/loongarch/simd.md (muh): New code attribute mapping > any_extend to smul_highpart or umul_highpart. > (mul3_highpart): New define_insn. > * config/loongarch/lsx.md (UNSPEC_LSX_VMUH_S): Remove. > (UNSPEC_LSX_VMUH_U): Remove. > (lsx_vmuh_s_): Remove. > (lsx_vmuh_u_): Remove. > * config/loongarch/lasx.md (UNSPEC_LASX_XVMUH_S): Remove. > (UNSPEC_LASX_XVMUH_U): Remove. > (lasx_xvmuh_s_): Remove. > (lasx_xvmuh_u_): Remove. > * config/loongarch/loongarch-builtins.cc (CODE_FOR_lsx_vmuh_b): > Redefine to standard pattern name. > (CODE_FOR_lsx_vmuh_h): Likewise. > (CODE_FOR_lsx_vmuh_w): Likewise. > (CODE_FOR_lsx_vmuh_d): Likewise. > (CODE_FOR_lsx_vmuh_bu): Likewise. > (CODE_FOR_lsx_vmuh_hu): Likewise. > (CODE_FOR_lsx_vmuh_wu): Likewise. > (CODE_FOR_lsx_vmuh_du): Likewise. > (CODE_FOR_lasx_xvmuh_b): Likewise. > (CODE_FOR_lasx_xvmuh_h): Likewise. > (CODE_FOR_lasx_xvmuh_w): Likewise. > (CODE_FOR_lasx_xvmuh_d): Likewise. > (CODE_FOR_lasx_xvmuh_bu): Likewise. > (CODE_FOR_lasx_xvmuh_hu): Likewise. > (CODE_FOR_lasx_xvmuh_wu): Likewise. > (CODE_FOR_lasx_xvmuh_du): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/vect-muh.c: New test. > --- > gcc/config/loongarch/lasx.md | 22 ------------ > gcc/config/loongarch/loongarch-builtins.cc | 32 ++++++++--------- > gcc/config/loongarch/lsx.md | 22 ------------ > gcc/config/loongarch/simd.md | 16 +++++++++ > gcc/testsuite/gcc.target/loongarch/vect-muh.c | 36 +++++++++++++++++++ > 5 files changed, 68 insertions(+), 60 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/loongarch/vect-muh.c > > diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md > index d4a56c307c4..023a023b44e 100644 > --- a/gcc/config/loongarch/lasx.md > +++ b/gcc/config/loongarch/lasx.md > @@ -68,8 +68,6 @@ (define_c_enum "unspec" [ > UNSPEC_LASX_BRANCH > UNSPEC_LASX_BRANCH_V > > - UNSPEC_LASX_XVMUH_S > - UNSPEC_LASX_XVMUH_U > UNSPEC_LASX_MXVEXTW_U > UNSPEC_LASX_XVSLLWIL_S > UNSPEC_LASX_XVSLLWIL_U > @@ -2823,26 +2821,6 @@ (define_insn "neg2" > [(set_attr "type" "simd_logic") > (set_attr "mode" "")]) > > -(define_insn "lasx_xvmuh_s_" > - [(set (match_operand:ILASX 0 "register_operand" "=f") > - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") > - (match_operand:ILASX 2 "register_operand" "f")] > - UNSPEC_LASX_XVMUH_S))] > - "ISA_HAS_LASX" > - "xvmuh.\t%u0,%u1,%u2" > - [(set_attr "type" "simd_int_arith") > - (set_attr "mode" "")]) > - > -(define_insn "lasx_xvmuh_u_" > - [(set (match_operand:ILASX 0 "register_operand" "=f") > - (unspec:ILASX [(match_operand:ILASX 1 "register_operand" "f") > - (match_operand:ILASX 2 "register_operand" "f")] > - UNSPEC_LASX_XVMUH_U))] > - "ISA_HAS_LASX" > - "xvmuh.\t%u0,%u1,%u2" > - [(set_attr "type" "simd_int_arith") > - (set_attr "mode" "")]) > - > (define_insn "lasx_xvsllwil_s__" > [(set (match_operand: 0 "register_operand" "=f") > (unspec: [(match_operand:ILASX_WHB 1 "register_operand" "f") > diff --git a/gcc/config/loongarch/loongarch-builtins.cc b/gcc/config/loongarch/loongarch-builtins.cc > index cbd833aa283..a6fcc1c731e 100644 > --- a/gcc/config/loongarch/loongarch-builtins.cc > +++ b/gcc/config/loongarch/loongarch-builtins.cc > @@ -319,6 +319,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) > #define CODE_FOR_lsx_vmod_hu CODE_FOR_umodv8hi3 > #define CODE_FOR_lsx_vmod_wu CODE_FOR_umodv4si3 > #define CODE_FOR_lsx_vmod_du CODE_FOR_umodv2di3 > +#define CODE_FOR_lsx_vmuh_b CODE_FOR_smulv16qi3_highpart > +#define CODE_FOR_lsx_vmuh_h CODE_FOR_smulv8hi3_highpart > +#define CODE_FOR_lsx_vmuh_w CODE_FOR_smulv4si3_highpart > +#define CODE_FOR_lsx_vmuh_d CODE_FOR_smulv2di3_highpart > +#define CODE_FOR_lsx_vmuh_bu CODE_FOR_umulv16qi3_highpart > +#define CODE_FOR_lsx_vmuh_hu CODE_FOR_umulv8hi3_highpart > +#define CODE_FOR_lsx_vmuh_wu CODE_FOR_umulv4si3_highpart > +#define CODE_FOR_lsx_vmuh_du CODE_FOR_umulv2di3_highpart > #define CODE_FOR_lsx_vmul_b CODE_FOR_mulv16qi3 > #define CODE_FOR_lsx_vmul_h CODE_FOR_mulv8hi3 > #define CODE_FOR_lsx_vmul_w CODE_FOR_mulv4si3 > @@ -439,14 +447,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) > #define CODE_FOR_lsx_vfnmsub_s CODE_FOR_vfnmsubv4sf4_nmsub4 > #define CODE_FOR_lsx_vfnmsub_d CODE_FOR_vfnmsubv2df4_nmsub4 > > -#define CODE_FOR_lsx_vmuh_b CODE_FOR_lsx_vmuh_s_b > -#define CODE_FOR_lsx_vmuh_h CODE_FOR_lsx_vmuh_s_h > -#define CODE_FOR_lsx_vmuh_w CODE_FOR_lsx_vmuh_s_w > -#define CODE_FOR_lsx_vmuh_d CODE_FOR_lsx_vmuh_s_d > -#define CODE_FOR_lsx_vmuh_bu CODE_FOR_lsx_vmuh_u_bu > -#define CODE_FOR_lsx_vmuh_hu CODE_FOR_lsx_vmuh_u_hu > -#define CODE_FOR_lsx_vmuh_wu CODE_FOR_lsx_vmuh_u_wu > -#define CODE_FOR_lsx_vmuh_du CODE_FOR_lsx_vmuh_u_du > #define CODE_FOR_lsx_vsllwil_h_b CODE_FOR_lsx_vsllwil_s_h_b > #define CODE_FOR_lsx_vsllwil_w_h CODE_FOR_lsx_vsllwil_s_w_h > #define CODE_FOR_lsx_vsllwil_d_w CODE_FOR_lsx_vsllwil_s_d_w > @@ -588,6 +588,14 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) > #define CODE_FOR_lasx_xvmul_h CODE_FOR_mulv16hi3 > #define CODE_FOR_lasx_xvmul_w CODE_FOR_mulv8si3 > #define CODE_FOR_lasx_xvmul_d CODE_FOR_mulv4di3 > +#define CODE_FOR_lasx_xvmuh_b CODE_FOR_smulv32qi3_highpart > +#define CODE_FOR_lasx_xvmuh_h CODE_FOR_smulv16hi3_highpart > +#define CODE_FOR_lasx_xvmuh_w CODE_FOR_smulv8si3_highpart > +#define CODE_FOR_lasx_xvmuh_d CODE_FOR_smulv4di3_highpart > +#define CODE_FOR_lasx_xvmuh_bu CODE_FOR_umulv32qi3_highpart > +#define CODE_FOR_lasx_xvmuh_hu CODE_FOR_umulv16hi3_highpart > +#define CODE_FOR_lasx_xvmuh_wu CODE_FOR_umulv8si3_highpart > +#define CODE_FOR_lasx_xvmuh_du CODE_FOR_umulv4di3_highpart > #define CODE_FOR_lasx_xvclz_b CODE_FOR_clzv32qi2 > #define CODE_FOR_lasx_xvclz_h CODE_FOR_clzv16hi2 > #define CODE_FOR_lasx_xvclz_w CODE_FOR_clzv8si2 > @@ -697,14 +705,6 @@ AVAIL_ALL (lasx, ISA_HAS_LASX) > #define CODE_FOR_lasx_xvavgr_hu CODE_FOR_lasx_xvavgr_u_hu > #define CODE_FOR_lasx_xvavgr_wu CODE_FOR_lasx_xvavgr_u_wu > #define CODE_FOR_lasx_xvavgr_du CODE_FOR_lasx_xvavgr_u_du > -#define CODE_FOR_lasx_xvmuh_b CODE_FOR_lasx_xvmuh_s_b > -#define CODE_FOR_lasx_xvmuh_h CODE_FOR_lasx_xvmuh_s_h > -#define CODE_FOR_lasx_xvmuh_w CODE_FOR_lasx_xvmuh_s_w > -#define CODE_FOR_lasx_xvmuh_d CODE_FOR_lasx_xvmuh_s_d > -#define CODE_FOR_lasx_xvmuh_bu CODE_FOR_lasx_xvmuh_u_bu > -#define CODE_FOR_lasx_xvmuh_hu CODE_FOR_lasx_xvmuh_u_hu > -#define CODE_FOR_lasx_xvmuh_wu CODE_FOR_lasx_xvmuh_u_wu > -#define CODE_FOR_lasx_xvmuh_du CODE_FOR_lasx_xvmuh_u_du > #define CODE_FOR_lasx_xvssran_b_h CODE_FOR_lasx_xvssran_s_b_h > #define CODE_FOR_lasx_xvssran_h_w CODE_FOR_lasx_xvssran_s_h_w > #define CODE_FOR_lasx_xvssran_w_d CODE_FOR_lasx_xvssran_s_w_d > diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md > index c1c3719e383..537afaf9625 100644 > --- a/gcc/config/loongarch/lsx.md > +++ b/gcc/config/loongarch/lsx.md > @@ -64,8 +64,6 @@ (define_c_enum "unspec" [ > UNSPEC_LSX_VSRLR > UNSPEC_LSX_VSRLRI > UNSPEC_LSX_VSHUF > - UNSPEC_LSX_VMUH_S > - UNSPEC_LSX_VMUH_U > UNSPEC_LSX_VEXTW_S > UNSPEC_LSX_VEXTW_U > UNSPEC_LSX_VSLLWIL_S > @@ -2506,26 +2504,6 @@ (define_insn "vneg2" > [(set_attr "type" "simd_logic") > (set_attr "mode" "")]) > > -(define_insn "lsx_vmuh_s_" > - [(set (match_operand:ILSX 0 "register_operand" "=f") > - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") > - (match_operand:ILSX 2 "register_operand" "f")] > - UNSPEC_LSX_VMUH_S))] > - "ISA_HAS_LSX" > - "vmuh.\t%w0,%w1,%w2" > - [(set_attr "type" "simd_int_arith") > - (set_attr "mode" "")]) > - > -(define_insn "lsx_vmuh_u_" > - [(set (match_operand:ILSX 0 "register_operand" "=f") > - (unspec:ILSX [(match_operand:ILSX 1 "register_operand" "f") > - (match_operand:ILSX 2 "register_operand" "f")] > - UNSPEC_LSX_VMUH_U))] > - "ISA_HAS_LSX" > - "vmuh.\t%w0,%w1,%w2" > - [(set_attr "type" "simd_int_arith") > - (set_attr "mode" "")]) > - > (define_insn "lsx_vextw_s_d" > [(set (match_operand:V2DI 0 "register_operand" "=f") > (unspec:V2DI [(match_operand:V4SI 1 "register_operand" "f")] > diff --git a/gcc/config/loongarch/simd.md b/gcc/config/loongarch/simd.md > index f371e201127..79324183233 100644 > --- a/gcc/config/loongarch/simd.md > +++ b/gcc/config/loongarch/simd.md > @@ -187,6 +187,22 @@ (define_insn_and_split "fix_trunc2" > [(set_attr "type" "simd_fcvt") > (set_attr "mode" "")]) > > +;; vmuh.{b/h/w/d} > + > +(define_code_attr muh > + [(sign_extend "smul_highpart") > + (zero_extend "umul_highpart")]) > + > +(define_insn "mul3_highpart" > + [(set (match_operand:IVEC 0 "register_operand" "=f") > + (:IVEC (match_operand:IVEC 1 "register_operand" "f") > + (match_operand:IVEC 2 "register_operand" "f"))) > + (any_extend (const_int 0))] > + "" > + "vmuh.\t%0,%1,%2" > + [(set_attr "type" "simd_int_arith") > + (set_attr "mode" "")]) > + > ; The LoongArch SX Instructions. > (include "lsx.md") > > diff --git a/gcc/testsuite/gcc.target/loongarch/vect-muh.c b/gcc/testsuite/gcc.target/loongarch/vect-muh.c > new file mode 100644 > index 00000000000..a788840b23c > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/vect-muh.c > @@ -0,0 +1,36 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mlasx -O3" } */ > +/* { dg-final { scan-assembler "\tvmuh\.w\t" } } */ > +/* { dg-final { scan-assembler "\tvmuh\.wu\t" } } */ > +/* { dg-final { scan-assembler "\txvmuh\.w\t" } } */ > +/* { dg-final { scan-assembler "\txvmuh\.wu\t" } } */ > + > +int a[8], b[8], c[8]; > + > +void > +test1 (void) > +{ > + for (int i = 0; i < 4; i++) > + c[i] = ((long)a[i] * (long)b[i]) >> 32; > +} > + > +void > +test2 (void) > +{ > + for (int i = 0; i < 4; i++) > + c[i] = ((long)(unsigned)a[i] * (long)(unsigned)b[i]) >> 32; > +} > + > +void > +test3 (void) > +{ > + for (int i = 0; i < 8; i++) > + c[i] = ((long)a[i] * (long)b[i]) >> 32; > +} > + > +void > +test4 (void) > +{ > + for (int i = 0; i < 8; i++) > + c[i] = ((long)(unsigned)a[i] * (long)(unsigned)b[i]) >> 32; > +}