From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 32465398382A for ; Tue, 27 Jul 2021 21:06:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 32465398382A Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id 16RL3OLD196098; Tue, 27 Jul 2021 17:06:38 -0400 Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com with ESMTP id 3a2spe05k7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 17:06:38 -0400 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 16RL4bjs009970; Tue, 27 Jul 2021 21:06:37 GMT Received: from b03cxnp08027.gho.boulder.ibm.com (b03cxnp08027.gho.boulder.ibm.com [9.17.130.19]) by ppma02dal.us.ibm.com with ESMTP id 3a2362wbmq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jul 2021 21:06:36 +0000 Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08027.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 16RL6Zu417957332 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 27 Jul 2021 21:06:35 GMT Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E64CB78069; Tue, 27 Jul 2021 21:06:34 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9BD137805C; Tue, 27 Jul 2021 21:06:33 +0000 (GMT) Received: from lexx (unknown [9.171.17.235]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 27 Jul 2021 21:06:33 +0000 (GMT) Message-ID: Subject: Re: [PATCH 45/55] rs6000: Builtin expansion, part 2 From: will schmidt To: Bill Schmidt , gcc-patches@gcc.gnu.org Cc: segher@kernel.crashing.org Date: Tue, 27 Jul 2021 16:06:31 -0500 In-Reply-To: <76032999efd830fe06da8fa1c70478d56251b9b8.1623941442.git.wschmidt@linux.ibm.com> References: <76032999efd830fe06da8fa1c70478d56251b9b8.1623941442.git.wschmidt@linux.ibm.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5 (3.28.5-10.el7) Mime-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: fJXk0jaKpNb8yc-0AkkH-Z91IhuFnnBu X-Proofpoint-GUID: fJXk0jaKpNb8yc-0AkkH-Z91IhuFnnBu X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-27_14:2021-07-27, 2021-07-27 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 adultscore=0 priorityscore=1501 impostorscore=0 clxscore=1015 spamscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2107140000 definitions=main-2107270119 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 27 Jul 2021 21:06:42 -0000 On Thu, 2021-06-17 at 10:19 -0500, Bill Schmidt via Gcc-patches wrote: > 2021-03-05 Bill Schmidt > Hi, > gcc/ > * config/rs6000/rs6000-call.c (rs6000_invalid_new_builtin): > Implement. > (rs6000_expand_ldst_mask): Likewise. > (rs6000_init_builtins): Initialize altivec_builtin_mask_for_load. ok > --- > gcc/config/rs6000/rs6000-call.c | 101 +++++++++++++++++++++++++++++++- > 1 file changed, 100 insertions(+), 1 deletion(-) > > diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c > index 8693836cd5a..754cd46b1c1 100644 > --- a/gcc/config/rs6000/rs6000-call.c > +++ b/gcc/config/rs6000/rs6000-call.c > @@ -11671,6 +11671,75 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode) > static void > rs6000_invalid_new_builtin (enum rs6000_gen_builtins fncode) > { > + size_t uns_fncode = (size_t) fncode; > + const char *name = rs6000_builtin_info_x[uns_fncode].bifname; > + > + switch (rs6000_builtin_info_x[uns_fncode].enable) > + { > + case ENB_P5: > + error ("%qs requires the %qs option", name, "-mcpu=power5"); > + break; > + case ENB_P6: > + error ("%qs requires the %qs option", name, "-mcpu=power6"); > + break; > + case ENB_ALTIVEC: > + error ("%qs requires the %qs option", name, "-maltivec"); > + break; > + case ENB_CELL: > + error ("%qs is only valid for the cell processor", name); > + break; > + case ENB_VSX: > + error ("%qs requires the %qs option", name, "-mvsx"); > + break; > + case ENB_P7: > + error ("%qs requires the %qs option", name, "-mcpu=power7"); > + break; > + case ENB_P7_64: > + error ("%qs requires the %qs option and either the %qs or %qs option", > + name, "-mcpu=power7", "-m64", "-mpowerpc64"); > + break; > + case ENB_P8: > + error ("%qs requires the %qs option", name, "-mcpu=power8"); > + break; > + case ENB_P8V: > + error ("%qs requires the %qs option", name, "-mpower8-vector"); > + break; > + case ENB_P9: > + error ("%qs requires the %qs option", name, "-mcpu=power9"); > + break; > + case ENB_P9_64: > + error ("%qs requires the %qs option and either the %qs or %qs option", > + name, "-mcpu=power9", "-m64", "-mpowerpc64"); > + break; > + case ENB_P9V: > + error ("%qs requires the %qs option", name, "-mpower9-vector"); > + break; > + case ENB_IEEE128_HW: > + error ("%qs requires ISA 3.0 IEEE 128-bit floating point", name); > + break; > + case ENB_DFP: > + error ("%qs requires the %qs option", name, "-mhard-dfp"); > + break; > + case ENB_CRYPTO: > + error ("%qs requires the %qs option", name, "-mcrypto"); > + break; > + case ENB_HTM: > + error ("%qs requires the %qs option", name, "-mhtm"); > + break; > + case ENB_P10: > + error ("%qs requires the %qs option", name, "-mcpu=power10"); > + break; > + case ENB_P10_64: > + error ("%qs requires the %qs option and either the %qs or %qs option", > + name, "-mcpu=power10", "-m64", "-mpowerpc64"); > + break; > + case ENB_MMA: > + error ("%qs requires the %qs option", name, "-mmma"); > + break; > + default: > + case ENB_ALWAYS: > + gcc_unreachable (); > + }; ok > } > > /* Target hook for early folding of built-ins, shamelessly stolen > @@ -14501,7 +14570,33 @@ rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, > rtx > rs6000_expand_ldst_mask (rtx target, tree arg0) > { > - return target; > + int icode2 = (BYTES_BIG_ENDIAN ? (int) CODE_FOR_altivec_lvsr_direct > + : (int) CODE_FOR_altivec_lvsl_direct); > + machine_mode tmode = insn_data[icode2].operand[0].mode; > + machine_mode mode = insn_data[icode2].operand[1].mode; > + rtx op, addr, pat; > + > + gcc_assert (TARGET_ALTIVEC); > + > + gcc_assert (POINTER_TYPE_P (TREE_TYPE (arg0))); > + op = expand_expr (arg0, NULL_RTX, Pmode, EXPAND_NORMAL); > + addr = memory_address (mode, op); > + /* We need to negate the address. */ > + op = gen_reg_rtx (GET_MODE (addr)); > + emit_insn (gen_rtx_SET (op, gen_rtx_NEG (GET_MODE (addr), addr))); > + op = gen_rtx_MEM (mode, op); > + > + if (target == 0 > + || GET_MODE (target) != tmode > + || ! (*insn_data[icode2].operand[0].predicate) (target, tmode)) > + target = gen_reg_rtx (tmode); > + > + pat = GEN_FCN (icode2) (target, op); > + if (!pat) > + return 0; > + emit_insn (pat); > + > + return target; ok > } > > /* Expand the CPU builtin in FCODE and store the result in TARGET. */ > @@ -15401,6 +15496,10 @@ rs6000_init_builtins (void) > /* Execute the autogenerated initialization code for builtins. */ > rs6000_autoinit_builtins (); > > + if (new_builtins_are_live) > + altivec_builtin_mask_for_load > + = rs6000_builtin_decls_x[RS6000_BIF_MASK_FOR_LOAD]; > + ok > if (new_builtins_are_live) > { > #ifdef SUBTARGET_INIT_BUILTINS