Applied Roger's proposed improvements with some changes:

Lengthy code is more convenient in avr.cc than in an insn
output function, and it makes it easy to work out the exact
instruction length.  Moreover, the code can handle shifts
with offset zero (cases of *and<mode>3 insns).

Passed with no new regressions on ATmega128.

Applied as https://gcc.gnu.org/r14-9317

Johann

--

AVR: Improve output of insn "*insv.any_shift.<mode>_split".

The instructions printed by insn "*insv.any_shift.<mode>_split" were
sub-optimal.  The code to print the improved output is lengthy and
performed by new function avr_out_insv.  As it turns out, the function
can also handle shift-offsets of zero, which is "*andhi3", "*andpsi3"
and "*andsi3".  Thus, these tree insns get a new 3-operand alternative
where the 3rd operand is an exact power of 2.

gcc/
         * config/avr/avr-protos.h (avr_out_insv): New proto.
         * config/avr/avr.cc (avr_out_insv): New function.
         (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
         (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
         * config/avr/avr.md (define_attr "adjust_len") Add insv.
         (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
         Add constraint alternative where the 3rd operand is a power
         of 2, and the source register may differ from the destination.
         (*insv.any_shift.<mode>_split): Call avr_out_insv to output
         instructions.  Set attr "length" to "insv".
         * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.

gcc/testsuite/
         * gcc.target/avr/torture/insv-anyshift-hi.c: New test.
         * gcc.target/avr/torture/insv-anyshift-si.c: New test.