Ulrich, Thanks for your comments, I have updated the patch accordingly. > > /* The SPE has an additional 32 synthetic registers, with DWARF debug > > info numbering for these registers starting at 1200. While > > eh_frame @@ -951,13 +952,14 @@ enum data_align { align_abi, align_opt, > > We must map them here to avoid huge unwinder tables mostly consisting > > of unused space. */ > > #define DWARF_REG_TO_UNWIND_COLUMN(r) \ > > - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) > > + ((r) >= FIRST_SPE_HIGH_REGNO ? ((r) - FIRST_SPE_HIGH_REGNO + > > + (DWARF_FRAME_REGISTERS - 32)) : (r)) > > As discussed above, this shouldn't change. Updated to handle first SPE high register too. #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) + ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r) Tested this patch on trunk [213030] & GCC v4.9.1 with ppc64 and didn't find any new regressions. Back ported this patch on GCC v4.8.3 e500v2 and tested with no new regressions PR target/60102 [libgcc] 2014-07-31 Rohit * config/rs6000/linux-unwind.h (ppc_fallback_frame_state): Update based on change in SPE high register numbers and 3 HTM registers. [gcc] 2014-07-31 Rohit * config/rs6000/rs6000.c (rs6000_reg_names) : Add SPE high register names. (alt_reg_names) : Likewise (rs6000_dwarf_register_span) : For SPE high registers, replace dwarf register numbers with GCC hard register numbers. (rs6000_init_dwarf_reg_sizes_extra) : Likewise. (rs6000_dbx_register_number): For SPE high registers, return dwarf register number for the corresponding GCC hard register number. * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER) : Update based on 32 newly added GCC hard register numbers for SPE high registers. (DWARF_FRAME_REGISTERS) : Likewise. (DWARF_REG_TO_UNWIND_COLUMN) : Likewise. (DWARF_FRAME_REGNUM) : Likewise. (FIXED_REGISTERS) : Likewise. (CALL_USED_REGISTERS) : Likewise. (CALL_REALLY_USED_REGISTERS) : Likewise. (REG_ALLOC_ORDER) : Likewise. (enum reg_class) : Likewise. (REG_CLASS_NAMES) : Likewise. (REG_CLASS_CONTENTS) : Likewise. (SPE_HIGH_REGNO_P) : New macro to identify SPE high registers. * gcc.target/powerpc/pr60102.c: New testcase. Please let me know if you have any further comments on the updated patch. Regards, Rohit