From: Jeff Law <jeffreyalaw@gmail.com>
To: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>,
"kito.cheng" <kito.cheng@gmail.com>,
Richard Biener <richard.guenther@gmail.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>, palmer <palmer@dabbelt.com>
Subject: Re: [PATCH] RISC-V: Fix bug reported by PR109535
Date: Tue, 18 Apr 2023 19:11:01 -0600 [thread overview]
Message-ID: <e2038723-d523-1f5f-f03d-183a91f2227c@gmail.com> (raw)
In-Reply-To: <82527A594505EAFC+20230419090408293747113@rivai.ai>
On 4/18/23 19:04, juzhe.zhong@rivai.ai wrote:
> The bug issue reported by google/highway project:
> (set(..........)
> (reg:QI s0)
> (reg:DI s0))
>
> The "avl" operand rtx = (reg:DI s0)
> count_occurrences return 1 however the actual regno occurrences should be 2.
> In this case, the VSETVL PASS will eliminate the use of (reg:DI s0) then
> file assertion in RTL_SSA.
> Instead, we should not eliminate "s0" dependency.
So these are not vector hard registers, but GPR hard registers. Meaning
you have to worry about even more things. Consider case on rv32 when
you ask to count (reg:QI s1) and there is a reference to (reg:DI s0).
Prior to reload you also have to worry about SUBREGs.
You probably need to be using refers_to_regno_p or something similar.
jeff
next prev parent reply other threads:[~2023-04-19 1:11 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-18 23:25 juzhe.zhong
2023-04-19 0:18 ` Kito Cheng
2023-04-19 0:56 ` Jeff Law
2023-04-19 1:04 ` juzhe.zhong
2023-04-19 1:11 ` Jeff Law [this message]
2023-04-19 1:29 ` juzhe.zhong
2023-04-19 5:43 ` Jeff Law
2023-04-19 10:45 ` juzhe.zhong
2023-04-19 1:34 ` juzhe.zhong
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