From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by sourceware.org (Postfix) with ESMTPS id EFC363858D33 for ; Tue, 14 Mar 2023 18:00:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EFC363858D33 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pj1-x102e.google.com with SMTP id l9-20020a17090a3f0900b0023d32684e7fso1659950pjc.1 for ; Tue, 14 Mar 2023 11:00:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1678816842; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=pE2qVWT4yBBq5Af2eZ5xiozbWvQSZPDlhAGeWRhCeRk=; b=mqNts1RIK7lQ5xYsIMmihvfIo9G7ZRf4B8nq6hPxEKP+4ub7DInQGnK+Hz0Mldn+Rz j2BC523PINQxBLbVb04SQD7sxp+PzTFoo0ob4gdfKfT7yUMhMUf2RKICoNkHaDr9/iQ5 Tl8YShssd/hcWAuvZw5jQ1ivUK3K34aB07sK07U4R3XHnIdWT/66EEOw6DIrey6+ku9J BrClrJPoNsinuLTv8As23jdMdyULyx24ctLZ6HkKxX2AosBXojHIdqL2QHswtrftkZHa XrHXXjH50VJzrAAF5suGw7o099xQ3sz2KJIHWi2EzMJsBlawviRkcNd8MGOayux0FQpd KDkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678816842; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pE2qVWT4yBBq5Af2eZ5xiozbWvQSZPDlhAGeWRhCeRk=; b=mcBVbjJtpjXmyHBYyZ2NTrlWS8d/qUusGxxoGM9uD3jQv0i99A8JjJg17xlKWoNHFD d+Q8a20OkIpC62+uMn7lxDoe8Z95sFeDwvctAd4qRieppPu1Vu/Iz1E0gjeaPz08lST0 n1fVY3yv7/PXLrXSxO7k3qnaptIGU/qUosSAVb5YSG2sJW24jN0DHcNevEaVmHxIwkIK RM769kTaxyg8orb2i92EC7faSUm6ambYrk9NIVU0DsVIcBvqYTrWTgcLS/R4gr+hkhuT HwtVJKWrQs1HhPjui725wNRXNruv9zL42ym2YfLjyZ/5oH7ywfdHVuf1wilPzZ1sXmkW 7/Qw== X-Gm-Message-State: AO0yUKXSv4XBkjF3cMaBtYhnYlxs9FeB2LyWi4zOyzuHzYbkoeWvIj9Q CQwzBjHkVjf/hCU1yYwt/8A= X-Google-Smtp-Source: AK7set/bAP2XiLPHBw9mlhIjbDFnrZ/7YgHpYP71MRitr5+6ibabLTtLDNyPXatcncBpxy+Tw+DL7Q== X-Received: by 2002:a17:902:db0e:b0:1a0:6bd4:ea9a with SMTP id m14-20020a170902db0e00b001a06bd4ea9amr2750756plx.16.1678816841870; Tue, 14 Mar 2023 11:00:41 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id p17-20020a170902e75100b0019a7c890c61sm2040835plf.252.2023.03.14.11.00.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Mar 2023 11:00:41 -0700 (PDT) Message-ID: Date: Tue, 14 Mar 2023 12:00:40 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Subject: Re: [PATCH v6] RISC-V: Add support for experimental zfa extension. Content-Language: en-US To: Jin Ma , gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, palmer@dabbelt.com References: <20230310124053.164-1-jinma@linux.alibaba.com> From: Jeff Law In-Reply-To: <20230310124053.164-1-jinma@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 3/10/23 05:40, Jin Ma via Gcc-patches wrote: > This patch adds the 'Zfa' extension for riscv, which is based on: > https://github.com/riscv/riscv-isa-manual/commit/d74d99e22d5f68832f70982d867614e2149a3bd7 > latest 'Zfa' change on the master branch of the RISC-V ISA Manual as > of this writing. > > The Wiki Page (details): > https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa > > The binutils-gdb for 'Zfa' extension: > https://sourceware.org/pipermail/binutils/2022-September/122938.html > > Implementation of zfa extension on LLVM: > https://reviews.llvm.org/rGc0947dc44109252fcc0f68a542fc6ef250d4d3a9 > > There are three points that need to be discussed here. > 1. According to riscv-spec, "The FCVTMO D.W.D instruction was added principally to > accelerate the processing of JavaScript Numbers.", so it seems that no implementation > is required in the compiler. > 2. The FROUND and FROUNDN instructions in this patch use related functions in the math > library, such as round, floor, ceil, etc. Since there is no interface for half-precision in > the math library, the instructions FROUN D.H and FROUNDN X.H have not been implemented for > the time being. Is it necessary to add a built-in interface belonging to riscv such as > __builtin_roundhf or __builtin_roundf16 to generate half floating point instructions? > 3. As far as I know, FMINM and FMAXM instructions correspond to C23 library function fminimum > and fmaximum. Therefore, I have not dealt with such instructions for the time being, but have > simply implemented the pattern of fminm3 and fmaxm3. Is it necessary to > add a built-in interface belonging to riscv such as__builtin_fminm to generate half > floating-point instructions? > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: Add zfa extension. > * config/riscv/constraints.md (Zf): Constrain the floating point number that the FLI instruction can load. > * config/riscv/iterators.md (round_pattern): New. > * config/riscv/predicates.md: Predicate the floating point number that the FLI instruction can load. > * config/riscv/riscv-opts.h (MASK_ZFA): New. > (TARGET_ZFA): New. > * config/riscv/riscv-protos.h (riscv_float_const_rtx_index_for_fli): Get the index of the > floating-point number that the FLI instruction can load. > * config/riscv/riscv.cc (find_index_in_array): New. > (riscv_float_const_rtx_index_for_fli): New. > (riscv_cannot_force_const_mem): Likewise. > (riscv_const_insns): Likewise. > (riscv_legitimize_const_move): Likewise. > (riscv_split_64bit_move_p): Exclude floating point numbers that can be loaded by FLI instructions. > (riscv_output_move): Likewise. > (riscv_memmodel_needs_release_fence): Likewise. > (riscv_print_operand): Likewise. > (riscv_secondary_memory_needed): Likewise. > * config/riscv/riscv.h (GP_REG_RTX_P): New. > * config/riscv/riscv.md (fminm3): New. > (fmaxm3): New. > (2): New. > (rint2): New. > (f_quiet4_zfa): New. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/zfa-fleq-fltq-rv32.c: New test. > * gcc.target/riscv/zfa-fleq-fltq.c: New test. > * gcc.target/riscv/zfa-fli-rv32.c: New test. > * gcc.target/riscv/zfa-fli-zfh-rv32.c: New test. > * gcc.target/riscv/zfa-fli-zfh.c: New test. > * gcc.target/riscv/zfa-fli.c: New test. > * gcc.target/riscv/zfa-fmovh-fmovp-rv32.c: New test. > * gcc.target/riscv/zfa-fround-rv32.c: New test. > * gcc.target/riscv/zfa-fround.c: New test. This needs to wait for gcc-14 IMHO. jeff