From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 129320 invoked by alias); 27 Jun 2017 14:01:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 128805 invoked by uid 89); 27 Jun 2017 14:01:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 27 Jun 2017 14:01:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DD7D9344; Tue, 27 Jun 2017 07:01:02 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 055E13F41F; Tue, 27 Jun 2017 07:01:01 -0700 (PDT) Subject: Re: [PATCH][AArch64] Fix ILP32 memory access To: Wilco Dijkstra , GCC Patches , James Greenhalgh Cc: nd References: From: "Richard Earnshaw (lists)" Message-ID: Date: Tue, 27 Jun 2017 14:01:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.1.1 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-SW-Source: 2017-06/txt/msg02033.txt.bz2 On 27/06/17 14:39, Wilco Dijkstra wrote: > This patch fixes a failure in gcc.target/aarch64/reload-valid-spoff.c > triggered by https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01367.html - > it supersedes https://gcc.gnu.org/ml/gcc-patches/2017-06/msg01907.html > as this fixes the root cause of the failure. > > In ILP32 all memory accesses must have Pmode as the base address, but > aarch64_expand_mov_immediate wasn't emitting a conversion in one case. > Besides fixing this add an assert that flags any MEM operands that are > not Pmode. > > Passes regress (with/without ilp32). OK for commit? > > ChangeLog: > 2017-06-27 Wilco Dijkstra > > * config/aarch64/aarch64 (aarch64_expand_mov_immediate): > Convert memory address to Pmode. Missing ChangeLog entry for the new assert. > -- > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index 329d244e9cf16dbdf849e5dd02b3999caf0cd5a7..9038748ba049ba589f067f3f04c31704fe673d2c 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -1958,6 +1958,8 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm) > gcc_assert (can_create_pseudo_p ()); > base = gen_reg_rtx (ptr_mode); > aarch64_expand_mov_immediate (base, XEXP (mem, 0)); > + if (ptr_mode != Pmode) > + base = convert_memory_address (Pmode, base); > mem = gen_rtx_MEM (ptr_mode, base); > } > > @@ -5207,6 +5209,7 @@ aarch64_print_operand (FILE *f, rtx x, int code) > > case MEM: > output_address (GET_MODE (x), XEXP (x, 0)); > + gcc_assert (GET_MODE (XEXP (x, 0)) == Pmode); > break; This is worthy of a comment. Something like "All memory references must be in Pmode, which is the natural mode of the machine. This remains the case even if ptr_mode is different, as for ILP32." Ok with those changes. R. > > case CONST: >