From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id A80B23858D32 for ; Mon, 3 Oct 2022 12:50:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A80B23858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=foss.arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0B8BC16F8; Mon, 3 Oct 2022 05:50:13 -0700 (PDT) Received: from [10.2.78.76] (unknown [10.2.78.76]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D02D43F73B; Mon, 3 Oct 2022 05:50:05 -0700 (PDT) Message-ID: Date: Mon, 3 Oct 2022 13:50:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH] arm: Add missing early clobber to MVE vrev64q_m patterns Content-Language: en-GB To: Christophe Lyon , gcc-patches@gcc.gnu.org References: <20221003104351.408835-1-christophe.lyon@arm.com> From: Richard Earnshaw In-Reply-To: <20221003104351.408835-1-christophe.lyon@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3497.2 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_LAZY_DOMAIN_SECURITY,KAM_SHORT,NICE_REPLY_A,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 03/10/2022 11:43, Christophe Lyon via Gcc-patches wrote: > Like the non-predicated vrev64q patterns, mve_vrev64q_m_ > and mve_vrev64q_m_f need an early clobber constraint, otherwise > we can generate an unpredictable instruction: > > Warning: 64-bit element size and same destination and source operands makes instruction UNPREDICTABLE > when calling vrevq64_m* with the same first and second arguments. > > Regression-tested on arm-none-eabi, bootstap in progress on > armv8l-unknown-linux-gnueabihf. > > OK for trunk? OK. R. > > Thanks, > > Christophe > > gcc/ChangeLog: > > * config/arm/mve.md: (mve_vrev64q_m_): Add early > clobber. > (mve_vrev64q_m_f): Likewise. > > gcc/testsuite/ChangeLog: > > * gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c: New test. > --- > gcc/config/arm/mve.md | 4 ++-- > .../arm/mve/intrinsics/vrev64q_m_s16-clobber.c | 17 +++++++++++++++++ > 2 files changed, 19 insertions(+), 2 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c > > diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md > index 714178609f7..62186f124da 100644 > --- a/gcc/config/arm/mve.md > +++ b/gcc/config/arm/mve.md > @@ -3503,7 +3503,7 @@ (define_insn "mve_vqshlq_m_r_" > ;; > (define_insn "mve_vrev64q_m_" > [ > - (set (match_operand:MVE_2 0 "s_register_operand" "=w") > + (set (match_operand:MVE_2 0 "s_register_operand" "=&w") > (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") > (match_operand:MVE_2 2 "s_register_operand" "w") > (match_operand: 3 "vpr_register_operand" "Up")] > @@ -4598,7 +4598,7 @@ (define_insn "mve_vrev32q_m_" > ;; > (define_insn "mve_vrev64q_m_f" > [ > - (set (match_operand:MVE_0 0 "s_register_operand" "=w") > + (set (match_operand:MVE_0 0 "s_register_operand" "=&w") > (unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "0") > (match_operand:MVE_0 2 "s_register_operand" "w") > (match_operand: 3 "vpr_register_operand" "Up")] > diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c > new file mode 100644 > index 00000000000..6464c96181d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_m_s16-clobber.c > @@ -0,0 +1,17 @@ > +/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ > +/* { dg-add-options arm_v8_1m_mve_fp } */ > +/* { dg-additional-options "-O2" } */ > + > +#include "arm_mve.h" > + > +int16x8_t > +foo (int16x8_t a, mve_pred16_t p) > +{ > + return vrev64q_m_s16 (a, a, p); > +} > + > +float16x8_t > +foo2 (float16x8_t a, mve_pred16_t p) > +{ > + return vrev64q_m_f16 (a, a, p); > +}