From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14069 invoked by alias); 20 Jul 2015 16:13:39 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 14045 invoked by uid 89); 20 Jul 2015 16:13:37 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL,BAYES_00,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=ham version=3.3.2 X-HELO: gcc1-power7.osuosl.org Received: from gcc1-power7.osuosl.org (HELO gcc1-power7.osuosl.org) (140.211.15.137) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES256-GCM-SHA384 encrypted) ESMTPS; Mon, 20 Jul 2015 16:13:34 +0000 Received: from gcc1-power7.osuosl.org (localhost [127.0.0.1]) by gcc1-power7.osuosl.org (8.14.6/8.14.6) with ESMTP id t6KGDWjP058214; Mon, 20 Jul 2015 09:13:32 -0700 Received: (from segher@localhost) by gcc1-power7.osuosl.org (8.14.6/8.14.6/Submit) id t6KGDWpN058211; Mon, 20 Jul 2015 09:13:32 -0700 From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Cc: dje.gcc@gmail.com, Segher Boessenkool Subject: [PATCH 2/3] Fix shift amount (GPR->SI) Date: Mon, 20 Jul 2015 16:14:00 -0000 Message-Id: In-Reply-To: References: In-Reply-To: References: X-IsSubscribed: yes X-SW-Source: 2015-07/txt/msg01667.txt.bz2 This changes the shift amount to always be SI (as it should be), not GPR. It doesn't matter for constant shifts, but there are some variable shifts as well, and consistency is good. No changelog, I'll fold it into the previous big patch, if approved. Segher --- gcc/config/rs6000/rs6000.md | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d8529f8..5727068 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3039,7 +3039,7 @@ (define_insn_and_split "*and3_imm_dot_shifted" (compare:CC (and:GPR (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r") - (match_operand:GPR 4 "const_int_operand" "n,n")) + (match_operand:SI 4 "const_int_operand" "n,n")) (match_operand:GPR 2 "const_int_operand" "n,n")) (const_int 0))) (clobber (match_scratch:GPR 0 "=r,r"))] @@ -3402,7 +3402,7 @@ (define_insn "*rotl3_mask" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (and:GPR (match_operator:GPR 4 "rotate_mask_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "reg_or_cint_operand" "rn")]) + (match_operand:SI 2 "reg_or_cint_operand" "rn")]) (match_operand:GPR 3 "const_int_operand" "n")))] "rs6000_is_valid_shift_mask (operands[3], operands[4], mode)" { @@ -3416,7 +3416,7 @@ (define_insn_and_split "*rotl3_mask_dot" (compare:CC (and:GPR (match_operator:GPR 4 "rotate_mask_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")]) + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")]) (match_operand:GPR 3 "const_int_operand" "n,n")) (const_int 0))) (clobber (match_scratch:GPR 0 "=r,r"))] @@ -3447,7 +3447,7 @@ (define_insn_and_split "*rotl3_mask_dot2" (compare:CC (and:GPR (match_operator:GPR 4 "rotate_mask_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r,r") - (match_operand:GPR 2 "reg_or_cint_operand" "rn,rn")]) + (match_operand:SI 2 "reg_or_cint_operand" "rn,rn")]) (match_operand:GPR 3 "const_int_operand" "n,n")) (const_int 0))) (set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") @@ -3482,7 +3482,7 @@ (define_insn "*rotl3_insert" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (ior:GPR (and:GPR (match_operator:GPR 4 "rotate_mask_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "const_int_operand" "n")]) + (match_operand:SI 2 "const_int_operand" "n")]) (match_operand:GPR 3 "const_int_operand" "n")) (and:GPR (match_operand:GPR 5 "gpc_reg_operand" "0") (match_operand:GPR 6 "const_int_operand" "n"))))] @@ -3502,7 +3502,7 @@ (define_insn "*rotl3_insert_2" (match_operand:GPR 6 "const_int_operand" "n")) (and:GPR (match_operator:GPR 4 "rotate_mask_operator" [(match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "const_int_operand" "n")]) + (match_operand:SI 2 "const_int_operand" "n")]) (match_operand:GPR 3 "const_int_operand" "n"))))] "rs6000_is_valid_insert_mask (operands[3], operands[4], mode) && UINTVAL (operands[3]) + UINTVAL (operands[6]) + 1 == 0" @@ -3517,7 +3517,7 @@ (define_insn "*rotl3_insert_3" (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0") (match_operand:GPR 4 "const_int_operand" "n")) (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "const_int_operand" "n"))))] + (match_operand:SI 2 "const_int_operand" "n"))))] "INTVAL (operands[2]) == exact_log2 (UINTVAL (operands[4]) + 1)" { if (mode == SImode) @@ -3532,7 +3532,7 @@ (define_insn "*rotl3_insert_4" (ior:GPR (and:GPR (match_operand:GPR 3 "gpc_reg_operand" "0") (match_operand:GPR 4 "const_int_operand" "n")) (lshiftrt:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "const_int_operand" "n"))))] + (match_operand:SI 2 "const_int_operand" "n"))))] "mode == SImode && GET_MODE_PRECISION (mode) == INTVAL (operands[2]) + exact_log2 (-UINTVAL (operands[4]))" @@ -3552,9 +3552,9 @@ (define_insn "*rotl3_insert_4" (define_split [(set (match_operand:GPR 0 "gpc_reg_operand") (ior:GPR (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand") - (match_operand:GPR 3 "const_int_operand")) + (match_operand:SI 3 "const_int_operand")) (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand") - (match_operand:GPR 4 "const_int_operand"))))] + (match_operand:SI 4 "const_int_operand"))))] "can_create_pseudo_p () && INTVAL (operands[3]) + INTVAL (operands[4]) >= GET_MODE_PRECISION (mode)" @@ -3576,9 +3576,9 @@ (define_split (define_split [(set (match_operand:GPR 0 "gpc_reg_operand") (ior:GPR (lshiftrt:GPR (match_operand:GPR 2 "gpc_reg_operand") - (match_operand:GPR 4 "const_int_operand")) + (match_operand:SI 4 "const_int_operand")) (ashift:GPR (match_operand:GPR 1 "gpc_reg_operand") - (match_operand:GPR 3 "const_int_operand"))))] + (match_operand:SI 3 "const_int_operand"))))] "can_create_pseudo_p () && INTVAL (operands[3]) + INTVAL (operands[4]) >= GET_MODE_PRECISION (mode)" -- 1.8.1.4