From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id 35A1F3836645 for ; Thu, 26 May 2022 07:01:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 35A1F3836645 Received: from pps.filterd (m0098413.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 24Q48bE9027579; Thu, 26 May 2022 07:01:46 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g9wxt6h4m-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 May 2022 07:01:45 +0000 Received: from m0098413.ppops.net (m0098413.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 24Q68ek6005046; Thu, 26 May 2022 07:01:45 GMT Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0b-001b2d01.pphosted.com (PPS) with ESMTPS id 3g9wxt6h42-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 May 2022 07:01:45 +0000 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 24Q6Z7h9014200; Thu, 26 May 2022 07:01:43 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma02fra.de.ibm.com with ESMTP id 3g9s6m8qa9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 26 May 2022 07:01:43 +0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 24Q6lVWF54657378 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 26 May 2022 06:47:31 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3E2D04C04E; Thu, 26 May 2022 07:01:41 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7D9B74C046; Thu, 26 May 2022 07:01:39 +0000 (GMT) Received: from [9.197.252.204] (unknown [9.197.252.204]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Thu, 26 May 2022 07:01:39 +0000 (GMT) Message-ID: Date: Thu, 26 May 2022 15:01:37 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.6.1 Subject: Re: [PATCH, rs6000] Clean up the option_mask defines (part 1) Content-Language: en-US To: will schmidt Cc: GCC Patches , David Edelsohn , Segher Boessenkool References: <6591013b62270c39c912f0c13c4cd12ffbaf75a2.camel@vnet.ibm.com> <338badbf-d784-76fb-95f2-58f6aa7ffae7@linux.ibm.com> From: "Kewen.Lin" In-Reply-To: <338badbf-d784-76fb-95f2-58f6aa7ffae7@linux.ibm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-TM-AS-GCONF: 00 X-Proofpoint-GUID: UEJlLI2eFnBU_GUXX5BwM7ThrotN2fpX X-Proofpoint-ORIG-GUID: MJrcGC143ethQg_jhcivVcb9GB5s57vy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-26_02,2022-05-25_02,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1015 malwarescore=0 phishscore=0 mlxscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2204290000 definitions=main-2205260033 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, NICE_REPLY_A, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 May 2022 07:01:49 -0000 on 2022/5/26 14:12, Kewen.Lin via Gcc-patches wrote: > Hi Will, > > on 2022/5/26 04:25, will schmidt via Gcc-patches wrote: >> [PATCH, rs6000] Clean up the option_mask defines >> >> Hi, >> >> We have an assortment of MASK and OPTION_MASK #defines throughout >> the rs6000 code, MASK_ALTIVEC and OPTION_MASK_ALTIVEC as an example. >> >> We currently #define the MASK_ entries to their OPTION_MASK_ >> equivalents so the two names could be used interchangeably. >> >> The mapping is in place from when we switched from using >> target_flags to rs6000_isa_flags via >> commit 4d9675496a28ef6184f2a9c3ac5e6e3ea63606c1 in 2012. >> >> This patch converts the references for most of the lingering MASK_* >> values to OPTION_MASK_* and removes the now redundant defines. >> > > Nice, thanks for the cleanup! > >> I have split this into multiple parts due to size. >> > > I guess they can be bootstrapped & regressed incrementally? > > I found there are still some masks left: > > MASK_POWERPC64, MASK_64BIT and MASK_LITTLE_ENDIAN. > > Is there one part 4 for them? Or is there some particular reason > not to clean up them? > aha, I see. Those three are conditional definitions, I agree it's better to leave them alone. :) >> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc >> index d4defc855d02..200bef3f822e 100644 >> --- a/gcc/config/rs6000/rs6000.cc >> +++ b/gcc/config/rs6000/rs6000.cc >> @@ -20727,15 +20727,15 @@ rs6000_darwin_file_start (void) >> const char *arg; >> const char *name; >> HOST_WIDE_INT if_set; >> } mapping[] = { >> { "ppc64", "ppc64", MASK_64BIT }, >> - { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 }, >> + { "970", "ppc970", OPTION_MASK_PPC_GPOPT | OPTION_MASK_MFCRF | MASK_POWERPC64 }, Nit: This line is too long. >> { "power4", "ppc970", 0 }, >> { "G5", "ppc970", 0 }, >> { "7450", "ppc7450", 0 }, >> - { "7400", "ppc7400", MASK_ALTIVEC }, >> + { "7400", "ppc7400", OPTION_MASK_ALTIVEC }, >> { "G4", "ppc7400", 0 }, >> { "750", "ppc750", 0 }, >> { "740", "ppc750", 0 }, >> { "G3", "ppc750", 0 }, >> { "604e", "ppc604e", 0 }, ... >> /* Builtin targets. For now, we reuse the masks for those options that are in >> target flags, and pick a random bit for ldbl128, which isn't in >> target_flags. */ Nit: Some of these BTM lines below exceed 80 characters, a few already existed previously. >> #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ >> -#define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ >> -#define RS6000_BTM_CMPB MASK_CMPB /* ISA 2.05: compare bytes. */ >> +#define RS6000_BTM_ALTIVEC OPTION_MASK_ALTIVEC /* VMX/altivec vectors. */ >> +#define RS6000_BTM_CMPB OPTION_MASK_CMPB /* ISA 2.05: compare bytes. */ >> #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ >> #define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ >> #define RS6000_BTM_P9_VECTOR MASK_P9_VECTOR /* ISA 3.0 vector. */ >> #define RS6000_BTM_P9_MISC MASK_P9_MISC /* ISA 3.0 misc. non-vector */ >> -#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ >> +#define RS6000_BTM_CRYPTO OPTION_MASK_CRYPTO /* crypto funcs. */ >> #define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ >> -#define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ >> -#define RS6000_BTM_FRES MASK_PPC_GFXOPT /* FRES instruction. */ >> -#define RS6000_BTM_FRSQRTE MASK_PPC_GFXOPT /* FRSQRTE instruction. */ >> -#define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ >> +#define RS6000_BTM_FRE OPTION_MASK_POPCNTB /* FRE instruction. */ >> +#define RS6000_BTM_FRES OPTION_MASK_PPC_GFXOPT /* FRES instruction. */ >> +#define RS6000_BTM_FRSQRTE OPTION_MASK_PPC_GFXOPT /* FRSQRTE instruction. */ >> +#define RS6000_BTM_FRSQRTES OPTION_MASK_POPCNTB /* FRSQRTES instruction. */ >> #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ >> -#define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ >> +#define RS6000_BTM_CELL OPTION_MASK_FPRND /* Target is cell powerpc. */ >> #define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ >> #define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ >> #define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */ >> #define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */ >> #define RS6000_BTM_POWERPC64 MASK_POWERPC64 /* 64-bit registers. */ BR, Kewen BR, Kewen